[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 17/94] target/sparc: Merge gen_fcond with only caller
From: |
Richard Henderson |
Subject: |
[PULL 17/94] target/sparc: Merge gen_fcond with only caller |
Date: |
Wed, 25 Oct 2023 17:14:12 -0700 |
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2664db302d..b8d51d6d64 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1309,19 +1309,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
}
}
-static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
-{
- DisasCompare cmp;
- gen_fcompare(&cmp, cc, cond);
-
- /* The interface is to return a boolean in r_dst. */
- if (cmp.is_bool) {
- tcg_gen_mov_tl(r_dst, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
- }
-}
-
// Inverted logic
static const TCGCond gen_tcg_cond_reg[8] = {
TCG_COND_NEVER, /* reserved */
@@ -2992,6 +2979,7 @@ TRANS(BPcc, 64, do_bpcc, a)
static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
+ DisasCompare cmp;
if (gen_trap_ifnofpu(dc)) {
return true;
@@ -3003,7 +2991,13 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
return advance_jump_uncond_always(dc, a->a, target);
default:
flush_cond(dc);
- gen_fcond(cpu_cond, a->cc, a->cond);
+
+ gen_fcompare(&cmp, a->cc, a->cond);
+ if (cmp.is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp.c1);
+ } else {
+ tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
+ }
return advance_jump_cond(dc, a->a, target);
}
}
--
2.34.1
- [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree, (continued)
- [PULL 13/94] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/25
- [PULL 11/94] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/25
- [PULL 12/94] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/25
- [PULL 06/94] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/25
- [PATCH 13/29] tcg/i386: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 06/29] tcg/optimize: Handle TCG_COND_TST{EQ,NE}, Richard Henderson, 2023/10/25
- [PATCH 18/29] tcg/sparc64: Hoist read of tcg_cond_to_rcond, Richard Henderson, 2023/10/25
- [PULL 19/94] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/25
- [PULL 20/94] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/25
- [PULL 16/94] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/25
- [PULL 17/94] target/sparc: Merge gen_fcond with only caller,
Richard Henderson <=
- [PATCH 17/29] tcg/sparc64: Implement tcg_out_extrl_i64_i32, Richard Henderson, 2023/10/25
- [PULL 08/94] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/25
- [PULL 21/94] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/25
- [PATCH 22/29] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel, Richard Henderson, 2023/10/25
- [PATCH 23/29] tcg/ppc: Create tcg_out_and_rc, Richard Henderson, 2023/10/25
- [PULL 22/94] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/25
- [PULL 24/94] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/25
- [PATCH 21/29] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc, Richard Henderson, 2023/10/25
- [PULL 26/94] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/25
- [PULL 34/94] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/25