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[PATCH v3 52/88] target/hppa: Implement SHRPD
From: |
Richard Henderson |
Subject: |
[PATCH v3 52/88] target/hppa: Implement SHRPD |
Date: |
Wed, 1 Nov 2023 18:29:40 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 6 ++-
target/hppa/translate.c | 97 ++++++++++++++++++++++++++++------------
2 files changed, 72 insertions(+), 31 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 7b51f39b9e..6f0c3f6ea5 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -332,8 +332,10 @@ addbi 101011 ..... ..... ... ........... . .
@rib_cf f=1
# Shift, Extract, Deposit
####
-shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
-shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
+shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5
+shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0
+shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \
+ d=1 cpos=%cpos6_11
extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5
extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 533e29879e..897b44d7e3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3279,34 +3279,64 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
return do_cbranch(ctx, a->disp, a->n, &cond);
}
-static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
+static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
{
- TCGv_reg dest;
+ TCGv_reg dest, src2;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
+ src2 = load_gpr(ctx, a->r2);
if (a->r1 == 0) {
- tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2));
- tcg_gen_shr_reg(dest, dest, cpu_sar);
+ if (a->d) {
+ tcg_gen_shr_reg(dest, src2, cpu_sar);
+ } else {
+ TCGv_reg tmp = tcg_temp_new();
+
+ tcg_gen_ext32u_reg(dest, src2);
+ tcg_gen_andi_reg(tmp, cpu_sar, 31);
+ tcg_gen_shr_reg(dest, dest, tmp);
+ }
} else if (a->r1 == a->r2) {
- TCGv_i32 t32 = tcg_temp_new_i32();
- TCGv_i32 s32 = tcg_temp_new_i32();
+ if (a->d) {
+ tcg_gen_rotr_reg(dest, src2, cpu_sar);
+ } else {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ TCGv_i32 s32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
- tcg_gen_trunc_reg_i32(s32, cpu_sar);
- tcg_gen_rotr_i32(t32, t32, s32);
- tcg_gen_extu_i32_reg(dest, t32);
+ tcg_gen_trunc_reg_i32(t32, src2);
+ tcg_gen_trunc_reg_i32(s32, cpu_sar);
+ tcg_gen_andi_i32(s32, s32, 31);
+ tcg_gen_rotr_i32(t32, t32, s32);
+ tcg_gen_extu_i32_reg(dest, t32);
+ }
} else {
- TCGv_i64 t = tcg_temp_new_i64();
- TCGv_i64 s = tcg_temp_new_i64();
+ TCGv_reg src1 = load_gpr(ctx, a->r1);
- tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
- tcg_gen_extu_reg_i64(s, cpu_sar);
- tcg_gen_shr_i64(t, t, s);
- tcg_gen_trunc_i64_reg(dest, t);
+ if (a->d) {
+ TCGv_reg t = tcg_temp_new();
+ TCGv_reg n = tcg_temp_new();
+
+ tcg_gen_xori_reg(n, cpu_sar, 63);
+ tcg_gen_shl_reg(t, src2, n);
+ tcg_gen_shli_reg(t, t, 1);
+ tcg_gen_shr_reg(dest, src1, cpu_sar);
+ tcg_gen_or_reg(dest, dest, t);
+ } else {
+ TCGv_i64 t = tcg_temp_new_i64();
+ TCGv_i64 s = tcg_temp_new_i64();
+
+ tcg_gen_concat_reg_i64(t, src2, src1);
+ tcg_gen_extu_reg_i64(s, cpu_sar);
+ tcg_gen_andi_i64(s, s, 31);
+ tcg_gen_shr_i64(t, t, s);
+ tcg_gen_trunc_i64_reg(dest, t);
+ }
}
save_gpr(ctx, a->t, dest);
@@ -3318,31 +3348,40 @@ static bool trans_shrpw_sar(DisasContext *ctx,
arg_shrpw_sar *a)
return nullify_end(ctx);
}
-static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
+static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
{
- unsigned sa = 31 - a->cpos;
+ unsigned width, sa;
TCGv_reg dest, t2;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
+ width = a->d ? 64 : 32;
+ sa = width - 1 - a->cpos;
+
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
if (a->r1 == 0) {
- tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
- } else if (TARGET_REGISTER_BITS == 32) {
+ tcg_gen_extract_reg(dest, t2, sa, width - sa);
+ } else if (width == TARGET_REGISTER_BITS) {
tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
- } else if (a->r1 == a->r2) {
- TCGv_i32 t32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, t2);
- tcg_gen_rotri_i32(t32, t32, sa);
- tcg_gen_extu_i32_reg(dest, t32);
} else {
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
- tcg_gen_shri_i64(t64, t64, sa);
- tcg_gen_trunc_i64_reg(dest, t64);
+ assert(!a->d);
+ if (a->r1 == a->r2) {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_reg_i32(t32, t2);
+ tcg_gen_rotri_i32(t32, t32, sa);
+ tcg_gen_extu_i32_reg(dest, t32);
+ } else {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
+ tcg_gen_shri_i64(t64, t64, sa);
+ tcg_gen_trunc_i64_reg(dest, t64);
+ }
}
save_gpr(ctx, a->t, dest);
--
2.34.1
- [PATCH v3 49/88] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, (continued)
- [PATCH v3 49/88] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, Richard Henderson, 2023/11/01
- [PATCH v3 51/88] target/hppa: Implement EXTRD, Richard Henderson, 2023/11/01
- [PATCH v3 57/88] target/hppa: Remove TARGET_REGISTER_BITS, Richard Henderson, 2023/11/01
- [PATCH v3 55/88] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/11/01
- [PATCH v3 69/88] target/hppa: Implement PERMH, Richard Henderson, 2023/11/01
- [PATCH v3 71/88] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/11/01
- [PATCH v3 59/88] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/11/01
- [PATCH v3 64/88] target/hppa: Implement HSUB, Richard Henderson, 2023/11/01
- [PATCH v3 46/88] target/hppa: Decode d for cmpb instructions, Richard Henderson, 2023/11/01
- [PATCH v3 50/88] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/11/01
- [PATCH v3 52/88] target/hppa: Implement SHRPD,
Richard Henderson <=
- [PATCH v3 53/88] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/11/01
- [PATCH v3 54/88] target/hppa: Implement STDBY, Richard Henderson, 2023/11/01
- [PATCH v3 60/88] target/hppa: Adjust vmstate_env for pa2.0 tlb, Richard Henderson, 2023/11/01
- [PATCH v3 73/88] include/hw/elf: Remove truncating signed casts, Richard Henderson, 2023/11/01
- [PATCH v3 61/88] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/11/01
- [PATCH v3 77/88] target/hppa: Add pa2.0 cpu local tlb flushes, Richard Henderson, 2023/11/01
- [PATCH v3 65/88] target/hppa: Implement HAVG, Richard Henderson, 2023/11/01
- [PATCH v3 62/88] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64, Richard Henderson, 2023/11/01
- [PATCH v3 67/88] target/hppa: Implement HSHLADD, HSHRADD, Richard Henderson, 2023/11/01
- [PATCH v3 75/88] linux-user/hppa: Drop EXCP_DUMP from handled exceptions, Richard Henderson, 2023/11/01