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[PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu
From: |
Alistair Francis |
Subject: |
[PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion |
Date: |
Tue, 7 Nov 2023 12:29:14 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Use the recently added riscv_cpu_accelerator_compatible() to filter
unavailable CPUs for a given accelerator. At this moment this is the
case for a QEMU built with KVM and TCG support querying a binary running
with TCG:
qemu-system-riscv64 -S -M virt,accel=tcg -display none
-qmp tcp:localhost:1234,server,wait=off
./qemu/scripts/qmp/qmp-shell localhost:1234
(QEMU) query-cpu-model-expansion type=full model={"name":"host"}
{"error": {"class": "GenericError", "desc": "'host' CPU not available with
tcg"}}
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/riscv-qmp-cmds.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index 5b2d186c83..2f2dbae7c8 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -31,6 +31,8 @@
#include "qapi/qobject-input-visitor.h"
#include "qapi/visitor.h"
#include "qom/qom-qobject.h"
+#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "cpu-qom.h"
#include "cpu.h"
@@ -63,6 +65,17 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error
**errp)
return cpu_list;
}
+static void riscv_check_if_cpu_available(RISCVCPU *cpu, Error **errp)
+{
+ if (!riscv_cpu_accelerator_compatible(cpu)) {
+ g_autofree char *name = riscv_cpu_get_name(cpu);
+ const char *accel = kvm_enabled() ? "kvm" : "tcg";
+
+ error_setg(errp, "'%s' CPU not available with %s", name, accel);
+ return;
+ }
+}
+
static void riscv_obj_add_qdict_prop(Object *obj, QDict *qdict_out,
const char *name)
{
@@ -161,6 +174,13 @@ CpuModelExpansionInfo
*qmp_query_cpu_model_expansion(CpuModelExpansionType type,
obj = object_new(object_class_get_name(oc));
+ riscv_check_if_cpu_available(RISCV_CPU(obj), &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ object_unref(obj);
+ return NULL;
+ }
+
if (qdict_in) {
riscv_cpuobj_validate_qdict_in(obj, model->props, qdict_in,
&local_err);
--
2.41.0
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., (continued)
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit, Alistair Francis, 2023/11/06
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max', Alistair Francis, 2023/11/06
- [PULL 14/49] qapi,risc-v: add query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion, Alistair Francis, 2023/11/06
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06
- [PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible(), Alistair Francis, 2023/11/06
- [PULL 20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset, Alistair Francis, 2023/11/06
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion,
Alistair Francis <=
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 19/49] Add epmp to extensions list and rename it to smepmp, Alistair Francis, 2023/11/06
- [PULL 23/49] target/riscv/kvm: add zicntr reg, Alistair Francis, 2023/11/06
- [PULL 24/49] target/riscv: add zihpm extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 25/49] target/riscv/kvm: add zihpm reg, Alistair Francis, 2023/11/06
- [PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot, Alistair Francis, 2023/11/06
- [PULL 27/49] target/riscv: correct csr_ops[CSR_MSECCFG], Alistair Francis, 2023/11/06
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, Alistair Francis, 2023/11/06
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, Alistair Francis, 2023/11/06
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06