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[PATCH v2 4/6] target/riscv: Add pointer masking tb flags
From: |
Alexey Baturo |
Subject: |
[PATCH v2 4/6] target/riscv: Add pointer masking tb flags |
Date: |
Sun, 24 Dec 2023 04:48:10 +0000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 15 +++++++++------
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +++++
3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c607a94bba..038b86db4b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -538,14 +538,17 @@ FIELD(TB_FLAGS, VILL, 14, 1)
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 16, 2)
-FIELD(TB_FLAGS, VTA, 18, 1)
-FIELD(TB_FLAGS, VMA, 19, 1)
+/* If pointer masking should be applied and address sign extended */
+FIELD(TB_FLAGS, PM_PMM, 18, 2)
+FIELD(TB_FLAGS, PM_SIGNEXTEND, 20, 1)
+FIELD(TB_FLAGS, VTA, 21, 1)
+FIELD(TB_FLAGS, VMA, 22, 1)
/* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 20, 1)
+FIELD(TB_FLAGS, ITRIGGER, 23, 1)
/* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
-FIELD(TB_FLAGS, PRIV, 22, 2)
-FIELD(TB_FLAGS, AXL, 24, 2)
+FIELD(TB_FLAGS, VIRT_ENABLED, 24, 1)
+FIELD(TB_FLAGS, PRIV, 25, 2)
+FIELD(TB_FLAGS, AXL, 27, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 47f325294e..7c33369cf1 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
RISCVCPU *cpu = env_archcpu(env);
RISCVExtStatus fs, vs;
uint32_t flags = 0;
+ bool pm_signext = !riscv_cpu_bare_mode(env);
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
@@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
*pflags = flags;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6b4b9a671c..1eb501e0d3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -103,6 +103,9 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
+ /* pointer masking extension */
+ uint8_t pm_pmm;
+ bool pm_signext;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
+ ctx->pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
+ ctx->pm_signext = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
--
2.34.1
- [PATCH v2 0/6] Pointer Masking update for Zjpm v0.8, Alexey Baturo, 2023/12/23
- [PATCH v2 1/6] target/riscv: Remove obsolete pointer masking extension code., Alexey Baturo, 2023/12/23
- [PATCH v2 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8, Alexey Baturo, 2023/12/23
- [PATCH v2 4/6] target/riscv: Add pointer masking tb flags,
Alexey Baturo <=
- [PATCH v2 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alexey Baturo, 2023/12/23
- [PATCH v2 5/6] target/riscv: Update address modify functions to take into account pointer masking, Alexey Baturo, 2023/12/23
- [PATCH v2 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alexey Baturo, 2023/12/23