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[PULL 41/65] target/riscv/tcg: handle profile MISA bits
From: |
Alistair Francis |
Subject: |
[PULL 41/65] target/riscv/tcg: handle profile MISA bits |
Date: |
Wed, 10 Jan 2024 18:57:09 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.
Now that we're setting profile MISA bits, one can use the rv64i CPU to boot
Linux using the following options:
-cpu rv64i,rva22u64=true,rv39=true,s=true,zifencei=true
In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are
mandatory), is implemented, rv64i will be able to boot Linux loading
rva22s64 and no additional flags.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index dd8f49b2a6..9fba3e8143 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -946,6 +946,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, const
char *name,
profile->user_set = true;
profile->enabled = value;
+ for (i = 0; misa_bits[i] != 0; i++) {
+ uint32_t bit = misa_bits[i];
+
+ if (!(profile->misa_ext & bit)) {
+ continue;
+ }
+
+ if (bit == RVI && !profile->enabled) {
+ /*
+ * Disabling profiles will not disable the base
+ * ISA RV64I.
+ */
+ continue;
+ }
+
+ g_hash_table_insert(misa_ext_user_opts,
+ GUINT_TO_POINTER(bit),
+ (gpointer)value);
+ riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
+ }
+
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
--
2.43.0
- [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT, (continued)
- [PULL 24/65] hw/riscv/virt-acpi-build.c: Add PLIC in MADT, Alistair Francis, 2024/01/10
- [PULL 25/65] hw/riscv/virt.c: fix the interrupts-extended property format of PLIC, Alistair Francis, 2024/01/10
- [PULL 26/65] target/riscv: Add support for Zacas extension, Alistair Francis, 2024/01/10
- [PULL 18/65] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT, Alistair Francis, 2024/01/10
- [PULL 27/65] disas/riscv: Add amocas.[w,d,q] instructions, Alistair Francis, 2024/01/10
- [PULL 28/65] docs/system/riscv: document acpi parameter of virt machine, Alistair Francis, 2024/01/10
- [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks, Alistair Francis, 2024/01/10
- [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions, Alistair Francis, 2024/01/10
- [PULL 32/65] target/riscv: add rv64i CPU, Alistair Francis, 2024/01/10
- [PULL 40/65] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Alistair Francis, 2024/01/10
- [PULL 41/65] target/riscv/tcg: handle profile MISA bits,
Alistair Francis <=
- [PULL 33/65] target/riscv: add zicbop extension flag, Alistair Francis, 2024/01/10
- [PULL 34/65] target/riscv/tcg: add 'zic64b' support, Alistair Francis, 2024/01/10
- [PULL 35/65] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Alistair Francis, 2024/01/10
- [PULL 37/65] target/riscv/kvm: add 'rva22u64' flag as unavailable, Alistair Francis, 2024/01/10
- [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU, Alistair Francis, 2024/01/10
- [PULL 36/65] target/riscv: add rva22u64 profile definition, Alistair Francis, 2024/01/10
- [PULL 38/65] target/riscv/tcg: add user flag for profile support, Alistair Francis, 2024/01/10
- [PULL 43/65] target/riscv/tcg: honor user choice for G MISA bits, Alistair Francis, 2024/01/10
- [PULL 39/65] target/riscv/tcg: add MISA user options hash, Alistair Francis, 2024/01/10
- [PULL 42/65] target/riscv/tcg: add hash table insert helpers, Alistair Francis, 2024/01/10