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[PULL 28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits
From: |
Peter Maydell |
Subject: |
[PULL 28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits |
Date: |
Thu, 11 Jan 2024 11:04:52 +0000 |
FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the
feature is enabled, allow this bit to be written in HCR_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/cpu-features.h | 5 +++++
target/arm/helper.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 3a43c328d9e..7a590c824cf 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -844,6 +844,11 @@ static inline bool isar_feature_aa64_nv(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0;
}
+static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2;
+}
+
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 24751e05b24..e3e56539594 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5857,6 +5857,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_nv, cpu)) {
valid_mask |= HCR_NV | HCR_NV1 | HCR_AT;
}
+ if (cpu_isar_feature(aa64_nv2, cpu)) {
+ valid_mask |= HCR_NV2;
+ }
}
if (cpu_isar_feature(any_evt, cpu)) {
--
2.34.1
- [PULL 09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers, (continued)
[PULL 11/41] target/arm: Implement HCR_EL2.AT handling, Peter Maydell, 2024/01/11
[PULL 10/41] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV, Peter Maydell, 2024/01/11
[PULL 13/41] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set, Peter Maydell, 2024/01/11
[PULL 16/41] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0, Peter Maydell, 2024/01/11
[PULL 28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits,
Peter Maydell <=
[PULL 25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1, Peter Maydell, 2024/01/11
[PULL 23/41] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled, Peter Maydell, 2024/01/11
[PULL 15/41] target/arm: Record correct opcode fields in cpreg for E2H aliases, Peter Maydell, 2024/01/11
[PULL 34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff), Peter Maydell, 2024/01/11
[PULL 33/41] target/arm: Report VNCR_EL2 based faults correctly, Peter Maydell, 2024/01/11
[PULL 29/41] target/arm: Implement VNCR_EL2 register, Peter Maydell, 2024/01/11
[PULL 32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM, Peter Maydell, 2024/01/11
[PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC), Peter Maydell, 2024/01/11
[PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8), Peter Maydell, 2024/01/11
[PULL 12/41] target/arm: Enable trapping of ERET for FEAT_NV, Peter Maydell, 2024/01/11