qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 07/33] target: Uninline cpu_mmu_index()


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH 07/33] target: Uninline cpu_mmu_index()
Date: Sun, 28 Jan 2024 17:45:06 +0100
User-agent: Mozilla Thunderbird

On 28/1/24 17:41, Philippe Mathieu-Daudé wrote:
On 28/1/24 05:41, Richard Henderson wrote:
From: Anton Johansson <anjo@rev.ng>

Uninlines the target-defined cpu_mmu_index() function by moving its
definition to target/*/cpu.c.  This allows for compiling memory access
functions in accel/tcg/cputlb.c without having to know target specifics.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20240119144024.14289-13-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
  include/exec/cpu-common.h | 10 ++++++++++
  target/alpha/cpu.h        |  9 ---------
  target/arm/cpu.h          | 13 -------------
  target/avr/cpu.h          |  7 -------
  target/cris/cpu.h         |  4 ----
  target/hexagon/cpu.h      |  9 ---------
  target/hppa/cpu.h         | 13 -------------
  target/i386/cpu.h         |  7 -------
  target/loongarch/cpu.h    | 12 ------------
  target/m68k/cpu.h         |  4 ----
  target/microblaze/cpu.h   | 15 ---------------
  target/mips/cpu.h         |  5 -----
  target/nios2/cpu.h        |  6 ------
  target/openrisc/cpu.h     | 12 ------------
  target/ppc/cpu.h          |  8 --------
  target/riscv/cpu.h        |  3 ---
  target/rx/cpu.h           |  5 -----
  target/s390x/cpu.h        | 31 -------------------------------
  target/sh4/cpu.h          | 10 ----------
  target/sparc/cpu.h        | 28 ----------------------------
  target/tricore/cpu.h      |  5 -----
  target/xtensa/cpu.h       |  5 -----
  target/alpha/cpu.c        |  8 ++++++++
  target/arm/cpu.c          |  5 +++++
  target/avr/cpu.c          |  5 +++++
  target/cris/cpu.c         |  4 ++++
  target/hexagon/cpu.c      |  9 +++++++++
  target/hppa/cpu.c         | 13 +++++++++++++
  target/i386/cpu.c         |  7 +++++++
  target/loongarch/cpu.c    | 12 ++++++++++++
  target/m68k/cpu.c         |  5 +++++
  target/microblaze/cpu.c   | 16 ++++++++++++++++
  target/mips/cpu.c         |  5 +++++
  target/nios2/cpu.c        |  6 ++++++
  target/openrisc/cpu.c     | 12 ++++++++++++
  target/ppc/cpu.c          |  9 +++++++++
  target/riscv/cpu_helper.c |  2 +-
  target/rx/cpu.c           |  5 +++++
  target/s390x/cpu.c        | 31 +++++++++++++++++++++++++++++++
  target/sh4/cpu.c          | 13 +++++++++++++
  target/sparc/cpu.c        | 28 ++++++++++++++++++++++++++++
  target/tricore/cpu.c      |  5 +++++
  target/xtensa/cpu.c       |  4 ++++
  43 files changed, 213 insertions(+), 212 deletions(-)

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 3109c6b67d..4724135f30 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -34,6 +34,16 @@ void cpu_list_lock(void);
  void cpu_list_unlock(void);
  unsigned int cpu_list_generation_id_get(void);
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
+int cpu_mmu_index(CPUArchState *env, bool ifetch);
+
  void tcg_iommu_init_notifier_list(CPUState *cpu);
  void tcg_iommu_free_notifier_list(CPUState *cpu);

I'm kind of reluctant to use CPUArchState in a -common.h header
(except in include/hw/core/cpu.h::cpu_env).

Last Wednesday community call I mentioned to Anton I have a branch
going in the same direction he is taking, and suggested him to wait
to compare and unify our works.

My bad I suppose, I should have replied to Anton series cover
to update you about the plan discussed during that call.

Also, if "This allows for compiling memory access functions in
accel/tcg/cputlb.c without having to know target specifics." I'd
rather see the corresponding meson change in the same patch.



reply via email to

[Prev in Thread] Current Thread [Next in Thread]