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Re: [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT
From: |
Jinjie Ruan |
Subject: |
Re: [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT |
Date: |
Thu, 22 Feb 2024 11:50:46 +0800 |
User-agent: |
Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 |
On 2024/2/22 3:28, Richard Henderson wrote:
> On 2/21/24 03:08, Jinjie Ruan via wrote:
>> Support ALLINT msr access as follow:
>> mrs <xt>, ALLINT // read allint
>> msr ALLINT, <xt> // write allint with imm
>>
>> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
>> ---
>> target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index a3062cb2ad..211156d640 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -4618,6 +4618,31 @@ static void aa64_daif_write(CPUARMState *env,
>> const ARMCPRegInfo *ri,
>> env->daif = value & PSTATE_DAIF;
>> }
>> +static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo
>> *ri,
>> + uint64_t value)
>> +{
>> + env->allint = value & PSTATE_ALLINT;
>> +}
>> +
>> +static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo
>> *ri)
>> +{
>> + return env->allint & PSTATE_ALLINT;
>> +}
>> +
>> +static CPAccessResult aa64_allint_access(CPUARMState *env,
>> + const ARMCPRegInfo *ri, bool
>> isread)
>> +{
>> + if (arm_current_el(env) == 0) {
>> + return CP_ACCESS_TRAP_UNCATEGORIZED;
>> + }
>
> This is handled by .access PL1_RW.
>
>> +
>> + if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
>> + cpu_isar_feature(aa64_hcx, env_archcpu(env)) &&
>> + (env->cp15.hcrx_el2 & HCRX_TALLINT))
>> + return CP_ACCESS_TRAP_EL2;
>
> You should be using arm_hcrx_el2_eff(env).
> Missing braces.
I'll fix it, thank you!
>
>> @@ -5437,6 +5462,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>> .access = PL0_RW, .accessfn = aa64_daif_access,
>> .fieldoffset = offsetof(CPUARMState, daif),
>> .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
>> + { .name = "ALLINT", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3,
>> + .type = ARM_CP_NO_RAW,
>> + .access = PL1_RW, .accessfn = aa64_allint_access,
>> + .fieldoffset = offsetof(CPUARMState, allint),
>> + .writefn = aa64_allint_write, .readfn = aa64_allint_read,
>> + .resetfn = arm_cp_reset_ignore },
>
> You cannot add ALLINT here in v8_cp_reginfo[].
> Compare fgt_reginfo[], and how it is registered.
I'll fix it, thank you!
>
>
> r~
- Re: [RFC PATCH v2 06/22] target/arm: Add support for Non-maskable Interrupt, (continued)
- [RFC PATCH v2 03/22] target/arm: Add PSTATE.ALLINT, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 16/22] hw/intc/arm_gicv3: Implement GICD_INMIR, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 05/22] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 09/22] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Jinjie Ruan, 2024/02/21
- [RFC PATCH v2 07/22] target/arm: Add support for NMI event state, Jinjie Ruan, 2024/02/21
[RFC PATCH v2 17/22] hw/intc: Enable FEAT_GICv3_NMI Feature, Jinjie Ruan, 2024/02/21
[RFC PATCH v2 13/22] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/02/21
[RFC PATCH v2 21/22] hw/intc/arm_gicv3: Implement NMI interrupt prioirty, Jinjie Ruan, 2024/02/21