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[PATCH 2/8] target/ppc: Make divw[u] handler method decodetree compatibl
From: |
Chinmay Rath |
Subject: |
[PATCH 2/8] target/ppc: Make divw[u] handler method decodetree compatible. |
Date: |
Tue, 16 Apr 2024 12:09:21 +0530 |
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
target/ppc/translate.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c45547a770..be7d807e3c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1738,8 +1738,9 @@ static inline void gen_op_arith_add(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
}
-static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
- TCGv arg2, int sign, int compute_ov)
+static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret,
+ TCGv arg1, TCGv arg2, bool sign,
+ bool compute_ov, bool compute_rc0)
{
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -1773,7 +1774,7 @@ static inline void gen_op_arith_divw(DisasContext *ctx,
TCGv ret, TCGv arg1,
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
- if (unlikely(Rc(ctx->opcode) != 0)) {
+ if (unlikely(compute_rc0)) {
gen_set_Rc0(ctx, ret);
}
}
@@ -1783,7 +1784,7 @@ static void glue(gen_, name)(DisasContext *ctx)
\
{ \
gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
- sign, compute_ov); \
+ sign, compute_ov, Rc(ctx->opcode)); \
}
/* divwu divwu. divwuo divwuo. */
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
--
2.39.3
- [PATCH 0/8] target/ppc: Move fixed-point insns to decodetree., Chinmay Rath, 2024/04/16
- [PATCH 1/8] target/ppc: Move mul{li, lw, lwo, hw, hwu} instructions to decodetree., Chinmay Rath, 2024/04/16
- [PATCH 2/8] target/ppc: Make divw[u] handler method decodetree compatible.,
Chinmay Rath <=
- [PATCH 3/8] target/ppc: Move divw[u, e, eu] instructions to decodetree., Chinmay Rath, 2024/04/16
- [PATCH 4/8] target/ppc: Move neg, darn, mod{sw, uw} to decodetree., Chinmay Rath, 2024/04/16
- [PATCH 5/8] target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree., Chinmay Rath, 2024/04/16
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