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Re: [Qemu-ppc] [Qemu-devel] [PATCH] Set an invalid-bits mask for each SP
From: |
Fabien Chouteau |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH] Set an invalid-bits mask for each SPE instructions |
Date: |
Fri, 07 Oct 2011 15:10:54 +0200 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.21) Gecko/20110831 Lightning/1.0b2 Mnenhy/0.8.4 Thunderbird/3.1.13 |
On 07/10/2011 14:40, Alexander Graf wrote:
> On 09/28/2011 05:54 PM, Fabien Chouteau wrote:
>> SPE instructions are defined by pairs. Currently, the invalid-bits mask is
>> set
>> for the first instruction, but the second one can have a different mask.
>>
>> example:
>> GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000,
>> PPC_SPE_DOUBLE),
>>
>> Signed-off-by: Fabien Chouteau<address@hidden>
>
> It certainly doesn't make the code more ugly than it was before :). Applied
> to my local ppc-next branch. I take it that you verified all the invalid
> masks are sane.
>
Yes I checked all the masks so they should be OK.
> There are some lines exceeding 80 characters, but I'm fairly sure they did
> before too. So I'll let this slip through for the sake of readability.
>
For these kind of definition lists the 80 characters limit can result in
very awful code.
Regards,
--
Fabien Chouteau