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[Qemu-ppc] [PATCH 42/48] mmu-hash*: Correctly mask RPN from hash PTE
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PATCH 42/48] mmu-hash*: Correctly mask RPN from hash PTE |
Date: |
Tue, 12 Mar 2013 21:31:44 +1100 |
BEHAVIOUR CHANGE
At present we take the whole of word 1 of the hash PTE as the real page
number used to calculate the translated address. This is incorrect,
because it leaves the flags from the low bits of PTE word 1 in place in the
rpm. We mostly get away with that because the value is later masked by
TARGET_PAGE_MASK.
More recent 64-bit CPUs also have a small number of flag bits (PP0 and
KEY) in the top bits of PTE word 1. Any guest which used those bits would
fail with the current code.
This patch fixes the problem by correctly masking out the RPN field of
PTE word 1. This is safe, even for older CPUs which didn't have PP0 and
KEY, because although the RPN notionally extended to the very top of PTE
word 1, none of those CPUs actually implemented that many real address
bits.
We add analogous masking to the 32-bit code, even though it also doesn't
have the high flag bits, for consistency and clarity.
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/mmu-hash32.c | 2 +-
target-ppc/mmu-hash64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index e5ee29b..07e9b8c 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -346,7 +346,7 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
target_ulong eaddr)
{
- hwaddr rpn = pte.pte1;
+ hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
hwaddr mask = ~TARGET_PAGE_MASK;
return (rpn & ~mask) | (eaddr & mask);
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 5e168d5..d986c0f 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -365,7 +365,7 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
target_ulong eaddr)
{
- hwaddr rpn = pte.pte1;
+ hwaddr rpn = pte.pte1 & HPTE64_R_RPN;
/* FIXME: Add support for SLLP extended page sizes */
int target_page_bits = (slb->vsid & SLB_VSID_L)
? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
--
1.7.10.4
- [Qemu-ppc] [PATCH 23/48] mmu-hash32: Split direct store segment handling into a helper, (continued)
- [Qemu-ppc] [PATCH 23/48] mmu-hash32: Split direct store segment handling into a helper, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 18/48] mmu-hash*: Reduce use of access_type, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 28/48] mmu-hash*: Remove permission checking from find_pte{32, 64}(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 01/48] target-ppc: Remove vestigial PowerPC 620 support, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 33/48] mmu-hash32: Clean up BAT matching logic, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 37/48] mmu-hash32: Remove nx from context structure, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 22/48] mmu-hash32: Split out handling of direct store segments, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 40/48] mmu-hash*: Clean up PTE flags update, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 34/48] mmu-hash32: Cleanup BAT lookup, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 19/48] mmu-hash64: Remove nx from mmu_ctx_hash64, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 42/48] mmu-hash*: Correctly mask RPN from hash PTE,
David Gibson <=
- [Qemu-ppc] [PATCH 16/48] mmu-hash*: Add header file for definitions, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 05/48] target-ppc: Disentangle pte_check(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 20/48] mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64}, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 43/48] mmu-hash*: Don't use full ppc_hash{32, 64}_translate() path for get_phys_page_debug(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 27/48] mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptes, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 10/48] target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_fault, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 12/48] target-ppc: Disentangle hash mmu helper functions, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 31/48] mmu-hash32: Remove odd pointer usage from BAT code, David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 21/48] mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}(), David Gibson, 2013/03/12
- [Qemu-ppc] [PATCH 13/48] target-ppc: Don't share get_pteg_offset() between 32 and 64-bit, David Gibson, 2013/03/12