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Re: [Qemu-ppc] [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VS
From: |
Richard Henderson |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions |
Date: |
Fri, 10 Jan 2014 13:29:53 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/10/2014 11:07 AM, Tom Musta wrote:
> +#define MV_VSR(name, tcgop1, tcgop2, target, source) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + if (xS(ctx->opcode) < 32) { \
> + if (unlikely(!ctx->fpu_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_FPU); \
> + return; \
> + } \
> + } else { \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + } \
> + TCGv_i64 tmp = tcg_temp_new_i64(); \
> + tcg_gen_##tcgop1(tmp, source); \
> + tcg_gen_##tcgop2(target, tmp); \
> + tcg_temp_free_i64(tmp); \
> +}
> +
> +
> +MV_VSR(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
> + cpu_vsrh(xS(ctx->opcode)))
> +MV_VSR(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
> + cpu_gpr[rA(ctx->opcode)])
> +MV_VSR(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
> + cpu_gpr[rA(ctx->opcode)])
> +#if defined(TARGET_PPC64)
> +MV_VSR(mfvsrd, mov_i64, mov_i64, cpu_gpr[rA(ctx->opcode)], \
> + cpu_vsrh(xS(ctx->opcode)))
> +MV_VSR(mtvsrd, mov_i64, mov_i64, cpu_vsrh(xT(ctx->opcode)), \
> + cpu_gpr[rA(ctx->opcode)])
> +#endif
Better to do this in one step:
mfcsrwz: tcg_gen_ext32u_tl
mtvsrwa: tcg_gen_ext_tl_i64
mtvsrwz: tcg_gen_extu_tl_i64
m[tf]vsrd: tcg_gen_mov_i64
r~
- [Qemu-ppc] [V6 PATCH 04/18] target-ppc: VSX Stage 4: Refactor stxsdx, (continued)
- [Qemu-ppc] [V6 PATCH 04/18] target-ppc: VSX Stage 4: Refactor stxsdx, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 05/18] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 06/18] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 07/18] target-ppc: VSX Stage 4: Add xsmulsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 14/18] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions, Tom Musta, 2014/01/10
- Re: [Qemu-ppc] [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions,
Richard Henderson <=
- [Qemu-ppc] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 10/18] target-ppc: VSX Stage 4: Add xssqrtsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 11/18] target-ppc: VSX Stage 4: add xsrsqrtesp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions, Tom Musta, 2014/01/10