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[Qemu-ppc] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and E
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR |
Date: |
Fri, 7 Mar 2014 00:34:05 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 7 ++++++-
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index dc0527b..99f10de 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -323,6 +323,7 @@ DEF_HELPER_3(vncipher, void, avr, avr, avr)
DEF_HELPER_3(vncipherlast, void, avr, avr, avr)
DEF_HELPER_3(vshasigmaw, void, avr, avr, i32)
DEF_HELPER_3(vshasigmad, void, avr, avr, i32)
+DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index e6a7ad0..63dde94 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2700,6 +2700,20 @@ void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a,
uint32_t st_six)
#undef ROTRu64
#undef EL_IDX
+void helper_vpermxor(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
+{
+ int i;
+ VECTOR_FOR_INORDER_I(i, u8) {
+ int indexA = c->u8[i] >> 4;
+ int indexB = c->u8[i] & 0xF;
+#if defined(HOST_WORDS_BIGENDIAN)
+ r->u8[i] = a->u8[indexA] ^ b->u8[indexB];
+#else
+ r->u8[i] = a->u8[15-indexA] ^ b->u8[15-indexB];
+#endif
+ }
+}
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e1dffdf..cf8f98a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7459,6 +7459,10 @@ static void gen_##op(DisasContext *ctx) \
VSHASIGMA(vshasigmaw)
VSHASIGMA(vshasigmad)
+GEN_VXFORM3(vpermxor, 22, 0xFF)
+GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
+ vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+
/*** VSX extension ***/
static inline TCGv_i64 cpu_vsrh(int n)
@@ -10111,7 +10115,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001,
PPC_ALTIVEC),
GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
-GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
@@ -10722,6 +10725,8 @@ GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21,
PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vshasigmaw, 1, 26),
GEN_VXFORM_207(vshasigmad, 1, 27),
+GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
+
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
--
1.8.1.4
- [Qemu-ppc] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, (continued)
- [Qemu-ppc] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 034/130] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 036/130] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 024/130] target-ppc: Add VSX ISA2.06 xrsqrte Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 008/130] kvm: Add a new machine option kvm-type, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 013/130] PPC: KVM: add support for LPCR, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 130/130] target-ppc: spapr: e500: fix to use cpu_dt_id, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 113/130] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 115/130] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR,
Alexander Graf <=
- [Qemu-ppc] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 125/130] target-ppc: Fix page table lookup with kvm enabled, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 121/130] PPC: sPAPR: Only use getpagesize() when we run with kvm, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 114/130] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 116/130] target-ppc: Altivec 2.07: AES Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 020/130] target-ppc: Add VSX ISA2.06 xmul Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 017/130] target-ppc: Add set_fprf Argument to fload_invalid_op_excp(), Alexander Graf, 2014/03/06