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[Qemu-ppc] [PATCH 08/77] ppc: Add number of threads per core to the proc
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 08/77] ppc: Add number of threads per core to the processor definition |
Date: |
Wed, 11 Nov 2015 11:27:21 +1100 |
Also use it to clamp the max SMT mode and ensure that the cpu_dt_id
are offset by that value in order to preserve consistency with the
HW implementations.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/cpu-qom.h | 1 +
target-ppc/translate_init.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index 6967a80..fef23fd 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -68,6 +68,7 @@ typedef struct PowerPCCPUClass {
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
+ uint32_t threads_per_core;
#if defined(TARGET_PPC64)
const struct ppc_segment_page_sizes *sps;
#endif
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c743eb1..1d402e1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8193,6 +8193,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x10000;
+ pcc->threads_per_core = 2;
}
static void powerpc_get_compat(Object *obj, Visitor *v,
@@ -8339,6 +8340,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->threads_per_core = 4;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8419,6 +8421,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->threads_per_core = 8;
}
#endif /* defined (TARGET_PPC64) */
@@ -9074,6 +9077,9 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error
**errp)
#endif
#if !defined(CONFIG_USER_ONLY)
+ if (max_smt > pcc->threads_per_core) {
+ max_smt = pcc->threads_per_core;
+ }
if (smp_threads > max_smt) {
error_setg(errp, "Cannot support more than %d threads on PPC with %s",
max_smt, kvm_enabled() ? "KVM" : "TCG");
@@ -9094,7 +9100,7 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error
**errp)
}
#if !defined(CONFIG_USER_ONLY)
- cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
+ cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * pcc->threads_per_core
+ (cs->cpu_index % smp_threads);
#endif
--
2.5.0
[Qemu-ppc] [PATCH 06/77] ppc: Add macros to register hypervisor mode SPRs, Benjamin Herrenschmidt, 2015/11/10
[Qemu-ppc] [PATCH 14/77] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Benjamin Herrenschmidt, 2015/11/10