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[Qemu-ppc] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s |
Date: |
Thu, 24 Mar 2016 15:30:47 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
We don't give them a KVM reg number to most of the registers yet as no
current KVM version supports HV mode. For DAWR and DAWRX, the KVM reg
number is needed since this register can be set by the guest via the
H_SET_MODE hypercall.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: squashed in patch 'ppc: Add KVM numbers to some P8 SPRs'
changed the commit log with a proposal of Thomas Huth
removed all hunks except those related to AMOR and DAWR* ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate_init.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index ebfce5d..3ecbd85 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -1105,6 +1105,11 @@ static void gen_spr_amr (CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_UAMOR, 0);
+ spr_register_hv(env, SPR_AMOR, "AMOR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0);
#endif /* !CONFIG_USER_ONLY */
}
#endif /* TARGET_PPC64 */
@@ -7491,6 +7496,20 @@ static void gen_spr_book3s_dbg(CPUPPCState *env)
KVM_REG_PPC_DABRX, 0x00000000);
}
+static void gen_spr_book3s_207_dbg(CPUPPCState *env)
+{
+ spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWR, 0x00000000);
+ spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAWRX, 0x00000000);
+}
+
static void gen_spr_970_dbg(CPUPPCState *env)
{
/* Breakpoints */
@@ -7960,6 +7979,8 @@ static void init_proc_book3s_64(CPUPPCState *env, int
version)
}
if (version < BOOK3S_CPU_POWER8) {
gen_spr_book3s_dbg(env);
+ } else {
+ gen_spr_book3s_207_dbg(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {
--
2.5.5
- [Qemu-ppc] [PULL 00/16] ppc-for-2.6 queue 20160324, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 11/16] ppc: Add dummy CIABR SPR, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s,
David Gibson <=
- [Qemu-ppc] [PULL 01/16] ppc64: set MSR_SF bit, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 09/16] ppc: Fix writing to AMR/UAMOR, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 03/16] ppc: Update SPR definitions, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 08/16] ppc: Initialize AMOR in PAPR mode, David Gibson, 2016/03/24
- [Qemu-ppc] [PULL 10/16] ppc: Add POWER8 IAMR register, David Gibson, 2016/03/24