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[Qemu-ppc] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in pr
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode |
Date: |
Tue, 7 Jun 2016 12:50:28 +1000 |
The architecture specifies that mtspr/mfspr on an unknown SPR number
should act as a nop in privileged mode.
I haven't removed the warning however as it can be useful for
diagnosing.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a3de142..dd0ecc8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4351,7 +4351,10 @@ static inline void gen_op_mfspr(DisasContext *ctx)
qemu_log("Trying to read invalid spr %d (0x%03x) at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
}
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ /* Only generate an exception in user space, otherwise this is a nop */
+ if (ctx->pr) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ }
}
}
@@ -4503,7 +4506,11 @@ static void gen_mtspr(DisasContext *ctx)
}
fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
- gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+
+ /* Only generate an exception in user space, otherwise this is a nop */
+ if (ctx->pr) {
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ }
}
}
--
2.5.5
- [Qemu-ppc] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 6/9] ppc: Fix mtmsr decoding, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode,
Benjamin Herrenschmidt <=
- [Qemu-ppc] [PATCH 7/9] ppc: Fix slbia decode, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers, Benjamin Herrenschmidt, 2016/06/06
- [Qemu-ppc] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode, Benjamin Herrenschmidt, 2016/06/06