[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode |
Date: |
Tue, 21 Jun 2016 23:48:50 +0200 |
From: Benjamin Herrenschmidt <address@hidden>
Under some circumstances, we need to direct ISI and DSI interrupts
at the hypervisor, turning them into HISI/HDSI, and using different
SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and
the corresponding VPM bits in LPCR.
This moves part of the code into helpers that are fixed to select
the right exception type and registers. On pre-P7 processors, LPCR
is 0 which provides the old behaviour of directing the interrupts
at the supervisor.
Thanks to Andrei Warkentin for finding a bug when HV=1
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: Merged a fix on POWERPC_EXCP_HDSI fixing the condition on
msr_hv, from Andrei Warkentin <address@hidden> ]
Signed-off-by: Cédric Le Goater <address@hidden>
---
target-ppc/mmu-hash64.c | 69 +++++++++++++++++++++++++++++++++++--------------
1 file changed, 50 insertions(+), 19 deletions(-)
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 668da5e22653..5b7b5e9eb10c 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -613,6 +613,47 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
return 0;
}
+static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
+ uint64_t error_code)
+{
+ bool vpm;
+
+ if (msr_ir) {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
+ } else {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ }
+ if (vpm && !msr_hv) {
+ cs->exception_index = POWERPC_EXCP_HISI;
+ } else {
+ cs->exception_index = POWERPC_EXCP_ISI;
+ }
+ env->error_code = error_code;
+}
+
+static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
+ uint64_t dsisr)
+{
+ bool vpm;
+
+ if (msr_dr) {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
+ } else {
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ }
+ if (vpm && !msr_hv) {
+ cs->exception_index = POWERPC_EXCP_HDSI;
+ env->spr[SPR_HDAR] = dar;
+ env->spr[SPR_HDSISR] = dsisr;
+ } else {
+ cs->exception_index = POWERPC_EXCP_DSI;
+ env->spr[SPR_DAR] = dar;
+ env->spr[SPR_DSISR] = dsisr;
+ }
+ env->error_code = 0;
+}
+
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
int rwx, int mmu_idx)
{
@@ -623,7 +664,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
hwaddr pte_offset;
ppc_hash_pte64_t pte;
int pp_prot, amr_prot, prot;
- uint64_t new_pte1;
+ uint64_t new_pte1, dsisr;
const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
hwaddr raddr;
@@ -657,26 +698,21 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
/* 3. Check for segment level no-execute violation */
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
- cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0x10000000;
+ ppc_hash64_set_isi(cs, env, 0x10000000);
return 1;
}
/* 4. Locate the PTE in the hash table */
pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
if (pte_offset == -1) {
+ dsisr = 0x40000000;
if (rwx == 2) {
- cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0x40000000;
+ ppc_hash64_set_isi(cs, env, dsisr);
} else {
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
- env->spr[SPR_DSISR] = 0x42000000;
- } else {
- env->spr[SPR_DSISR] = 0x40000000;
+ dsisr |= 0x02000000;
}
+ ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
}
return 1;
}
@@ -705,14 +741,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
/* Access right violation */
qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
if (rwx == 2) {
- cs->exception_index = POWERPC_EXCP_ISI;
- env->error_code = 0x08000000;
+ ppc_hash64_set_isi(cs, env, 0x08000000);
} else {
- target_ulong dsisr = 0;
-
- cs->exception_index = POWERPC_EXCP_DSI;
- env->error_code = 0;
- env->spr[SPR_DAR] = eaddr;
+ dsisr = 0;
if (need_prot[rwx] & ~pp_prot) {
dsisr |= 0x08000000;
}
@@ -722,7 +753,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
if (need_prot[rwx] & ~amr_prot) {
dsisr |= 0x00200000;
}
- env->spr[SPR_DSISR] = dsisr;
+ ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
}
return 1;
}
--
2.1.4
- [Qemu-ppc] [PATCH v2 01/10] ppc: Fix rfi/rfid/hrfi/... emulation, (continued)
[Qemu-ppc] [PATCH v2 02/10] ppc: define a default LPCR value, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 03/10] ppc: fix exception model for HV mode, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 04/10] ppc: Fix POWER7 and POWER8 exception definitions, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 05/10] ppc: Fix generation if ISI/DSI vs. HV mode,
Cédric Le Goater <=
[Qemu-ppc] [PATCH v2 06/10] ppc: Rework generation of priv and inval interrupts, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 07/10] ppc: Add real mode CI load/store instructions for P7 and P8, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 08/10] ppc: Turn a bunch of booleans from int to bool, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 09/10] ppc: Move exception generation code out of line, Cédric Le Goater, 2016/06/21
[Qemu-ppc] [PATCH v2 10/10] ppc: Add P7/P8 Power Management instructions, Cédric Le Goater, 2016/06/21