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[Qemu-ppc] [PULL 12/14] target-ppc: Return page shift from PTEG search
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 12/14] target-ppc: Return page shift from PTEG search |
Date: |
Tue, 5 Jul 2016 15:31:37 +1000 |
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it
didn't previously do. This means we're now double decoding the page size
because we check it int he fault path after ppc64_hash64_htab_lookup()
returns.
To avoid this duplication have ppc_hash64_pteg_search() and
ppc_hash64_htab_lookup() return the page size from the PTE and use that in
the callers instead of decoding again.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/mmu-hash64.c | 33 ++++++++-------------------------
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 07d3249..7c1b169 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -489,7 +489,7 @@ static unsigned hpte_page_shift(const struct
ppc_one_seg_page_size *sps,
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
ppc_slb_t *slb, target_ulong ptem,
- ppc_hash_pte64_t *pte)
+ ppc_hash_pte64_t *pte, unsigned *pshift)
{
CPUPPCState *env = &cpu->env;
int i;
@@ -508,7 +508,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu,
hwaddr hash,
/* This compares V, B, H (secondary) and the AVPN */
if (HPTE64_V_COMPARE(pte0, ptem)) {
- unsigned pshift = hpte_page_shift(slb->sps, pte0, pte1);
+ *pshift = hpte_page_shift(slb->sps, pte0, pte1);
/*
* If there is no match, ignore the PTE, it could simply
* be for a different segment size encoding and the
@@ -516,7 +516,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu,
hwaddr hash,
* potentially leave behind PTEs for the wrong base page
* size when demoting segments.
*/
- if (pshift == 0) {
+ if (*pshift == 0) {
continue;
}
/* We don't do anything with pshift yet as qemu TLB only deals
@@ -537,7 +537,7 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu,
hwaddr hash,
static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
ppc_slb_t *slb, target_ulong eaddr,
- ppc_hash_pte64_t *pte)
+ ppc_hash_pte64_t *pte, unsigned *pshift)
{
CPUPPCState *env = &cpu->env;
hwaddr pte_offset;
@@ -576,7 +576,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, vsid, ptem, hash);
- pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte);
+ pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte, pshift);
if (pte_offset == -1) {
/* Secondary PTEG lookup */
@@ -587,7 +587,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
" hash=" TARGET_FMT_plx "\n", env->htab_base,
env->htab_mask, vsid, ptem, ~hash);
- pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte);
+ pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte,
pshift);
}
return pte_offset;
@@ -714,7 +714,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
}
/* 4. Locate the PTE in the hash table */
- pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte);
+ pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
if (pte_offset == -1) {
dsisr = 0x40000000;
if (rwx == 2) {
@@ -730,18 +730,6 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr
eaddr,
qemu_log_mask(CPU_LOG_MMU,
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
- /* Validate page size encoding */
- apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
- if (!apshift) {
- error_report("Bad page size encoding in HPTE 0x%"PRIx64" - 0x%"PRIx64
- " @ 0x%"HWADDR_PRIx, pte.pte0, pte.pte1, pte_offset);
- /* Not entirely sure what the right action here, but machine
- * check seems reasonable */
- cs->exception_index = POWERPC_EXCP_MCHECK;
- env->error_code = 0;
- return 1;
- }
-
/* 5. Check access permissions */
pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
@@ -815,16 +803,11 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu,
target_ulong addr)
return -1;
}
- pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte);
+ pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
if (pte_offset == -1) {
return -1;
}
- apshift = hpte_page_shift(slb->sps, pte.pte0, pte.pte1);
- if (!apshift) {
- return -1;
- }
-
return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
& TARGET_PAGE_MASK;
}
--
2.7.4
- [Qemu-ppc] [PULL 00/14] ppc-for-2.7 queue 20160705 (v2), David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 03/14] ppc: simplify max_smt initialization in ppc_cpu_realizefn(), David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 12/14] target-ppc: Return page shift from PTEG search,
David Gibson <=
- [Qemu-ppc] [PULL 11/14] target-ppc: Simplify HPTE matching, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 06/14] vfio: Add host side DMA window capabilities, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 14/14] ppc/hash64: Fix support for LPCR:ISL, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 02/14] spapr: Ensure thread0 of CPU core is always realized first, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 01/14] ppc: Fix xsrdpi, xvrdpi and xvrspi rounding, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 09/14] ppc: simplify ppc_hash64_hpte_page_shift_noslb(), David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 10/14] target-ppc: Correct page size decoding in ppc_hash64_pteg_search(), David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 04/14] spapr_iommu: Realloc guest visible TCE table when starting/stopping listening, David Gibson, 2016/07/05
- [Qemu-ppc] [PULL 07/14] vfio/spapr: Create DMA window dynamically (SPAPR IOMMU v2), David Gibson, 2016/07/05