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Re: [Qemu-ppc] [RFC 4/6] target-ppc: add cmprb instruction
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC 4/6] target-ppc: add cmprb instruction |
Date: |
Mon, 18 Jul 2016 12:00:30 +1000 |
User-agent: |
Mutt/1.6.1 (2016-04-27) |
On Tue, Jul 12, 2016 at 11:33:20PM +0530, Nikunj A Dadhania wrote:
> ISA 3.0 Compare Ranged Byte instruction useful for
> isupper/islower/isaplha kind of operation.
At least until you have locale-aware versions of those...
> Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> target-ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 93c7c66..8de217f 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -817,6 +817,45 @@ static void gen_cmpli(DisasContext *ctx)
> }
> }
>
> +/* cmprb - range comparison: isupper, isaplha, islower*/
> +static void gen_cmprb(DisasContext *ctx)
> +{
> + TCGLabel *lab1 = gen_new_label();
> + TCGLabel *lab2 = gen_new_label();
> + TCGv src1 = tcg_temp_local_new();
> + TCGv src2 = tcg_temp_local_new();
> + TCGv src2lo = tcg_temp_local_new();
> + TCGv src2hi = tcg_temp_local_new();
> +
> + tcg_gen_andi_tl(src1, cpu_gpr[rA(ctx->opcode)], 0xFF);
> + tcg_gen_andi_tl(src2, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF);
> +
> + tcg_gen_andi_tl(src2lo, src2, 0xFF);
> + tcg_gen_shri_tl(src2hi, src2, 8);
> + tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
> +
> + tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab1);
> + tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab1);
> + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> + tcg_gen_br(lab2);
> + gen_set_label(lab1);
> +
> + if (ctx->opcode & 0x00200000) {
> + tcg_gen_shri_tl(src2hi, src2, 24);
> + tcg_gen_andi_tl(src2hi, src2hi, 0xFF);
> + tcg_gen_shri_tl(src2lo, src2, 16);
> + tcg_gen_andi_tl(src2lo, src2lo, 0xFF);
> + tcg_gen_brcond_tl(TCG_COND_GTU, src1, src2hi, lab2);
> + tcg_gen_brcond_tl(TCG_COND_LTU, src1, src2lo, lab2);
> + tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 1 << CRF_GT);
> + }
> + gen_set_label(lab2);
> + tcg_temp_free(src1);
> + tcg_temp_free(src2);
> + tcg_temp_free(src2lo);
> + tcg_temp_free(src2hi);
> +}
> +
> /* isel (PowerPC 2.03 specification) */
> static void gen_isel(DisasContext *ctx)
> {
> @@ -9898,6 +9937,7 @@ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000,
> PPC_INTEGER),
> GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
> +GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
> GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
> GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [RFC 2/6] target-ppc: Introduce POWER ISA 3.0 flag, (continued)
[Qemu-ppc] [RFC 6/6] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/12
[Qemu-ppc] [RFC 4/6] target-ppc: add cmprb instruction, Nikunj A Dadhania, 2016/07/12
[Qemu-ppc] [RFC 3/6] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/12