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Re: [Qemu-ppc] [PATCH 12/32] ppc: FP exceptions are always precise
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 12/32] ppc: FP exceptions are always precise |
Date: |
Wed, 27 Jul 2016 12:00:09 +1000 |
User-agent: |
Mutt/1.6.2 (2016-07-01) |
On Wed, Jul 27, 2016 at 08:21:06AM +1000, Benjamin Herrenschmidt wrote:
> We don't implement imprecise FP exceptions and using store_current
> which sets SRR1 to the *previous* instruction never makes sense
> for these. So let's be truthful and make them precise, which is
> allowed by the architecture.
I don't see any store_correct in the altered code, so the description
doesn't quite make sense to me.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> ---
> target-ppc/excp_helper.c | 11 ++++++-----
> target-ppc/translate.c | 1 -
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index f4b115e..91fdf4b 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -274,12 +274,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> env->error_code = 0;
> return;
> }
> +
> + /* FP exceptions always have NIP pointing to the faulting
> + * instruction, so always use store_next and claim we are
> + * precise in the MSR.
> + */
> msr |= 0x00100000;
> - if (msr_fe0 == msr_fe1) {
> - goto store_next;
> - }
> - msr |= 0x00010000;
> - break;
> + goto store_next;
> case POWERPC_EXCP_INVAL:
> LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
> msr |= 0x00080000;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index cb4e313..a05fed7 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2846,7 +2846,6 @@ static void gen_conditional_store(DisasContext *ctx,
> TCGv EA,
> int reg, int size)
> {
> TCGv t0 = tcg_temp_new();
> - uint32_t save_exception = ctx->exception;
Also, this appears to be an unrelated change.
> tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
> tcg_gen_movi_tl(t0, (size << 5) | reg);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [Qemu-devel] [PATCH 09/32] ppc: Make float_invalid_op_excp() pass the return address, (continued)
- [Qemu-ppc] [PATCH 15/32] ppc: Make tlb_fill() use new exception helper, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 13/32] ppc: Don't update NIP in lswi/lswx/stswi/stswx, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 10/32] ppc: Make float_check_status() pass the return address, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 12/32] ppc: FP exceptions are always precise, Benjamin Herrenschmidt, 2016/07/26
- Re: [Qemu-ppc] [PATCH 12/32] ppc: FP exceptions are always precise,
David Gibson <=
- [Qemu-ppc] [PATCH 11/32] ppc: Don't update the NIP in floating point generated code, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 08/32] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 03/32] ppc: Move classic fp ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 04/32] ppc: Move embedded spe ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 06/32] ppc: Move VMX ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 07/32] ppc: Move VSX ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 18/32] ppc: Don't update NIP in DCR access routines, Benjamin Herrenschmidt, 2016/07/26