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[Qemu-ppc] [PATCHv2 24/31] ppc: Handle unconditional (always/never) trap
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCHv2 24/31] ppc: Handle unconditional (always/never) traps at translation time |
Date: |
Wed, 27 Jul 2016 16:56:42 +1000 |
We don't need to call a helper for trap always and trap never
which are used by Linux under some circumstances.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
--
v2. Don't generate the helper call when trapping always
---
target-ppc/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 20c9cbb..a29c7ce 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3574,10 +3574,30 @@ static void gen_sc(DisasContext *ctx)
/*** Trap ***/
+/* Check for unconditional traps (always or never) */
+static bool check_unconditional_trap(DisasContext *ctx)
+{
+ /* Trap never */
+ if (TO(ctx->opcode) == 0) {
+ return true;
+ }
+ /* Trap always */
+ if (TO(ctx->opcode) == 31) {
+ gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ return true;
+ }
+ return false;
+}
+
/* tw */
static void gen_tw(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
+ TCGv_i32 t0;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3586,8 +3606,14 @@ static void gen_tw(DisasContext *ctx)
/* twi */
static void gen_twi(DisasContext *ctx)
{
- TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
- TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
+ TCGv t0;
+ TCGv_i32 t1;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_tl(SIMM(ctx->opcode));
+ t1 = tcg_const_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
@@ -3597,7 +3623,12 @@ static void gen_twi(DisasContext *ctx)
/* td */
static void gen_td(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
+ TCGv_i32 t0;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3606,8 +3637,14 @@ static void gen_td(DisasContext *ctx)
/* tdi */
static void gen_tdi(DisasContext *ctx)
{
- TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
- TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
+ TCGv t0;
+ TCGv_i32 t1;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_tl(SIMM(ctx->opcode));
+ t1 = tcg_const_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-ppc] [PATCHv2 14/31] ppc: Make tlb_fill() use new exception helper, (continued)
- [Qemu-ppc] [PATCHv2 14/31] ppc: Make tlb_fill() use new exception helper, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 16/31] ppc: Fix source NIP on SLB related interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 15/31] ppc: Rework NIP updates vs. exception generation, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 17/31] ppc: Don't update NIP in DCR access routines, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 21/31] ppc: Don't update NIP if not taking alignment exceptions, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 22/31] ppc: Don't update NIP in dcbz and lscbx, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 19/31] ppc: Don't update NIP BookE 2.06 tlbwe, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 18/31] ppc: Don't update NIP in facility unavailable interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 20/31] ppc: Don't update NIP on conditional trap instructions, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 23/31] ppc: Make alignment exceptions suck less, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 24/31] ppc: Handle unconditional (always/never) traps at translation time,
Benjamin Herrenschmidt <=
- [Qemu-ppc] [PATCHv2 25/31] ppc: Speed up dcbz, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 26/31] ppc: Fix CFAR updates, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 27/31] ppc: Avoid double translation for lvx/lvxl/stvx/stvxl, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 29/31] ppc: Use a helper to generate "LE unsupported" alignment interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 30/31] ppc: load/store multiple and string insns don't do LE, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 28/31] ppc: Don't set access_type on all load/stores on hash64, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-ppc] [PATCHv2 31/31] ppc: Speed up load/store multiple, Benjamin Herrenschmidt, 2016/07/27