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[Qemu-ppc] [PULL 10/66] target-ppc: add cnttzw[.] instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 10/66] target-ppc: add cnttzw[.] instruction |
Date: |
Tue, 6 Sep 2016 13:39:57 +1000 |
From: Nikunj A Dadhania <address@hidden>
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +++++
target-ppc/translate.c | 11 +++++++++++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0c29c01..9c79808 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 93e8dfa..02b6df3 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -145,6 +145,11 @@ target_ulong helper_cntlzw(target_ulong t)
return clz32(t);
}
+target_ulong helper_cnttzw(target_ulong t)
+{
+ return ctz32(t);
+}
+
#if defined(TARGET_PPC64)
target_ulong helper_cntlzd(target_ulong t)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 8eea692..b248453 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1583,6 +1583,16 @@ static void gen_cntlzw(DisasContext *ctx)
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
+
+/* cnttzw */
+static void gen_cnttzw(DisasContext *ctx)
+{
+ gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ }
+}
+
/* eqv & eqv. */
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
/* extsb & extsb. */
@@ -10057,6 +10067,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.7.4
- [Qemu-ppc] [PULL 41/66] ppc: Fix CFAR updates, (continued)
- [Qemu-ppc] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 53/66] target-ppc: add extswsli[.] instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 48/66] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 40/66] ppc: Speed up dcbz, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 27/66] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 64/66] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 01/66] xics_kvm: drop extra checking of kernel_xics_fd, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 05/66] target-ppc: adding addpcis instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 10/66] target-ppc: add cnttzw[.] instruction,
David Gibson <=
- [Qemu-ppc] [PULL 55/66] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 56/66] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 24/66] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 37/66] ppc: Don't update NIP in dcbz and lscbx, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 52/66] target-ppc: add vsrv instruction, David Gibson, 2016/09/05