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[Qemu-ppc] [PULL 27/44] target-ppc: convert st[16, 32, 64]r to use new m
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 27/44] target-ppc: convert st[16, 32, 64]r to use new macro |
Date: |
Thu, 22 Sep 2016 16:37:25 +1000 |
From: Nikunj A Dadhania <address@hidden>
Make byte-swap routines use the common GEN_QEMU_STORE macro
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 32 ++++++++++----------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 254ad40..60668c2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2510,6 +2510,9 @@ GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
+GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
+GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
+
#define GEN_QEMU_STORE_64(stop, op) \
static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
TCGv_i64 val, \
@@ -2521,6 +2524,10 @@ static void glue(gen_qemu_, glue(stop,
_i64))(DisasContext *ctx, \
GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
+#if defined(TARGET_PPC64)
+GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
+#endif
+
#define GEN_LD(name, ldop, opc, type) \
static void glue(gen_, name)(DisasContext *ctx)
\
{ \
@@ -2844,34 +2851,15 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
#if defined(TARGET_PPC64)
/* ldbrx */
GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
+/* stdbrx */
+GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
#endif /* TARGET_PPC64 */
/* sthbrx */
-static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
-
/* stwbrx */
-static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
-#if defined(TARGET_PPC64)
-/* stdbrx */
-static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
- tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
-}
-GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
-#endif /* TARGET_PPC64 */
-
/*** Integer load and store multiple ***/
/* lmw */
@@ -6619,7 +6607,7 @@ GEN_STS(stw, st32, 0x04, PPC_INTEGER)
#if defined(TARGET_PPC64)
GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
-GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
+GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
--
2.7.4
- [Qemu-ppc] [PULL 15/44] adb.c: correct several key assignments, (continued)
- [Qemu-ppc] [PULL 15/44] adb.c: correct several key assignments, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 09/44] qtest: replace strtoXX() by qemu_strtoXX(), David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 33/44] target-ppc: add stxsi[bh]x instruction, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 34/44] target-ppc: implement darn instruction, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 42/44] ppc/kvm: Mark 64kB page size support as disabled if not available, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 43/44] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 26/44] target-ppc: convert st64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 23/44] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 08/44] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 22/44] target-ppc: consolidate load operations, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 27/44] target-ppc: convert st[16, 32, 64]r to use new macro,
David Gibson <=
- [Qemu-ppc] [PULL 14/44] adb.c: add support for QKeyCode, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 25/44] target-ppc: consolidate store operations, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 41/44] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 24/44] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 30/44] target-ppc: consolidate store conditional, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 29/44] target-ppc: move out stqcx impementation, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 44/44] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 39/44] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 03/44] target-ppc: add vector insert instructions, David Gibson, 2016/09/22
- [Qemu-ppc] [PULL 05/44] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/22