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[Qemu-ppc] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II
From: |
Jose Ricardo Ziviani |
Subject: |
[Qemu-ppc] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II |
Date: |
Fri, 25 Nov 2016 01:53:29 -0200 |
v3:
- use decimal numbers instead of hex when appropriate
- set condition register flag to the new form
- fix bcdcfsq loops boundaries
v2:
- use div128 and mul64 functions to make code easier to understand
- fixed int128 neg
- improved functions bcdcpsgn and bcdsetsgn to do less work
than necessary
- rebased on ppc-for-2.9
This serie contains 4 new instructions for POWER9 ISA3.0
bcdcfsq.: Convert signed quadword to packed BCD
bcdctsq.: Convert packed BCD to signed quadword
bcdcpsgn.: Copy the sign of a register to another
bcdsetsgn.: Set the BCD sign according to a preferred sign
Jose Ricardo Ziviani (4):
target-ppc: Implement bcdcfsq. instruction
target-ppc: Implement bcdctsq. instruction
target-ppc: Implement bcdcpsgn. instruction
target-ppc: Implement bcdsetsgn. instruction
target-ppc/helper.h | 4 ++
target-ppc/int_helper.c | 120 ++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 25 ++++++++
target-ppc/translate/vmx-ops.inc.c | 2 +-
4 files changed, 150 insertions(+), 1 deletion(-)
--
2.7.4
- [Qemu-ppc] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II,
Jose Ricardo Ziviani <=
- [Qemu-ppc] [PATCH v3 1/4] target-ppc: Implement bcdcfsq. instruction, Jose Ricardo Ziviani, 2016/11/24
- [Qemu-ppc] [PATCH v3 2/4] target-ppc: Implement bcdctsq. instruction, Jose Ricardo Ziviani, 2016/11/24
- [Qemu-ppc] [PATCH v3 3/4] target-ppc: Implement bcdcpsgn. instruction, Jose Ricardo Ziviani, 2016/11/24
- [Qemu-ppc] [PATCH v3 4/4] target-ppc: Implement bcdsetsgn. instruction, Jose Ricardo Ziviani, 2016/11/24
- Re: [Qemu-ppc] [PATCH v3 0/4] POWER9 TCG enablements - BCD functions part II, David Gibson, 2016/11/24