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Re: [Qemu-ppc] [Qemu-devel] [PATCH 2/7] target-ppc: Implement unsigned q
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH 2/7] target-ppc: Implement unsigned quadword left/right shift and unit tests |
Date: |
Mon, 5 Dec 2016 12:56:39 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Sat, Dec 03, 2016 at 05:37:27PM -0800, Richard Henderson wrote:
> On 12/02/2016 09:00 PM, Jose Ricardo Ziviani wrote:
> > +++ b/include/qemu/host-utils.h
> > @@ -29,6 +29,33 @@
> > #include "qemu/bswap.h"
> >
> > #ifdef CONFIG_INT128
> > +static inline void urshift(uint64_t *plow, uint64_t *phigh, uint32_t shift)
> > +{
> > + __uint128_t val = ((__uint128_t)*phigh << 64) | *plow;
> > + val >>= (shift & 127);
> > + *phigh = val >> 64;
> > + *plow = val & 0xffffffffffffffff;
> > +}
> > +
> > +static inline void ulshift(uint64_t *plow, uint64_t *phigh,
> > + uint32_t shift, bool *overflow)
> > +{
> > + __uint128_t val = ((__uint128_t)*phigh << 64) | *plow;
> > +
> > + if (shift == 0) {
> > + return;
> > + }
> > +
> > + if (shift > 127 || (val >> (128 - (shift & 127))) != 0) {
> > + *overflow = true;
> > + }
> > +
> > + val <<= (shift & 127);
> > +
> > + *phigh = val >> 64;
> > + *plow = val & 0xffffffffffffffff;
> > +}
> > +
>
> This belongs in qemu/int128.h, not here. And certainly not predicated on
> CONFIG_INT128.
Is there actually any advantage to the __uint128_t based versions over
the 64-bit versions?
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[Qemu-ppc] [PATCH 3/7] target-ppc: Implement bcds. instruction, Jose Ricardo Ziviani, 2016/12/03
[Qemu-ppc] [PATCH 4/7] target-ppc: Implement bcdus. instruction, Jose Ricardo Ziviani, 2016/12/03
[Qemu-ppc] [PATCH 5/7] target-ppc: Implement bcdsr. instruction, Jose Ricardo Ziviani, 2016/12/03