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[Qemu-ppc] [PATCH 12/13] target-ppc: implement xscpsgnqp instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH 12/13] target-ppc: implement xscpsgnqp instruction |
Date: |
Mon, 5 Dec 2016 16:55:29 +0530 |
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/translate/vsx-impl.inc.c | 12 +++++++++++-
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index 560deaf..77f098b 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -642,9 +642,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
+ int xa; \
int xt = rD(ctx->opcode) + 32; \
int xb = rB(ctx->opcode) + 32; \
- TCGv_i64 xbh, xbl, sgm; \
+ TCGv_i64 xah, xbh, xbl, sgm; \
\
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
@@ -667,6 +668,14 @@ static void glue(gen_, name)(DisasContext *ctx)
\
tcg_gen_xor_i64(xbh, xbh, sgm); \
tcg_gen_xori_i64(xbl, xbl, 0); \
break; \
+ case OP_CPSGN: \
+ xah = tcg_temp_new_i64(); \
+ xa = rA(ctx->opcode) + 32; \
+ tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_temp_free_i64(xah); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -678,6 +687,7 @@ static void glue(gen_, name)(DisasContext *ctx)
\
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index d798edb..42e83d2 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -107,6 +107,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
+GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
- [Qemu-ppc] [PATCH 08/13] target-ppc: implement xxinsertw instruction, (continued)
- [Qemu-ppc] [PATCH 08/13] target-ppc: implement xxinsertw instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 10/13] target-ppc: implement xsabsqp/xsnabsqp instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 11/13] target-ppc: implement xsnegqp instruction, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 13/13] target-ppc: Add xxperm and xxpermr instructions, Nikunj A Dadhania, 2016/12/05
- [Qemu-ppc] [PATCH 12/13] target-ppc: implement xscpsgnqp instruction,
Nikunj A Dadhania <=
- Re: [Qemu-ppc] [PATCH ppc-for-2.9 00/13] POWER9 TCG enablements - part9, David Gibson, 2016/12/05