[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction |
Date: |
Thu, 2 Feb 2017 16:13:55 +1100 |
From: Nikunj A Dadhania <address@hidden>
xsxexpqp: VSX Scalar Extract Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 15 +++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 33ca177..228e2a5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1224,6 +1224,21 @@ static void gen_xsxexpdp(DisasContext *ctx)
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
}
+
+static void gen_xsxexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+ TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(xth, xbh, 48);
+ tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_movi_i64(xtl, 0);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 85d3b7d..87f1852 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,6 +115,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 064/107] target-ppc: Add xscvdpqp instruction, (continued)
- [Qemu-ppc] [PULL 064/107] target-ppc: Add xscvdpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 055/107] target-ppc: Use correct precision for FPRF setting, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 073/107] ppc: Implement bcdus. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 096/107] target/ppc: Remove unused POWERPC_FAMILY(POWER), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 072/107] ppc: Implement bcds. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 097/107] target/ppc/cpu-models: Fix/remove bad CPU aliases, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu class definition, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 107/107] hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction,
David Gibson <=
- [Qemu-ppc] [PULL 103/107] tcg/POWER9: NOOP the cp_abort instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02