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[Qemu-ppc] [PATCH v2 02/11] target/ppc: optimize gen_write_xer()
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v2 02/11] target/ppc: optimize gen_write_xer() |
Date: |
Wed, 22 Feb 2017 14:59:39 +0530 |
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3ba2616..b09e16f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3724,12 +3724,9 @@ static void gen_write_xer(TCGv src)
{
tcg_gen_andi_tl(cpu_xer, src,
~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
- tcg_gen_shri_tl(cpu_so, src, XER_SO);
- tcg_gen_shri_tl(cpu_ov, src, XER_OV);
- tcg_gen_shri_tl(cpu_ca, src, XER_CA);
- tcg_gen_andi_tl(cpu_so, cpu_so, 1);
- tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
- tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
}
/* mcrxr */
--
2.7.4
- [Qemu-ppc] [PATCH v2 00/11] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 01/11] target/ppc: move cpu_[read, write]_xer to cpu.c, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 03/11] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 02/11] target/ppc: optimize gen_write_xer(),
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
- [Qemu-ppc] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/22