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[Qemu-ppc] [PULL 24/48] ppc/pnv: create the ICP object under PnvCore
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 24/48] ppc/pnv: create the ICP object under PnvCore |
Date: |
Wed, 26 Apr 2017 17:00:10 +1000 |
From: Cédric Le Goater <address@hidden>
Each thread of a core is linked to an ICP. This allocates a PnvICPState
object before the PowerPCCPU object is realized and lets the XICSFabric
do the store under the 'intc' backlink when xics_cpu_setup() is
called.
This modeling removes the need of maintaining an array of ICP objects
under the PowerNV machine and also simplifies the XICSFabric icp_get()
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 2 ++
hw/ppc/pnv_core.c | 27 +++++++++++++++++++++++++--
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f3623ee..2add2ad 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -694,6 +694,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(pnv_core),
pcc->core_pir(chip, core_hwid),
"pir", &error_fatal);
+ object_property_add_const_link(OBJECT(pnv_core), "xics",
+ qdev_get_machine(), &error_fatal);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
&error_fatal);
object_unref(OBJECT(pnv_core));
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index d79d530..1b7ec70 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -25,6 +25,7 @@
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/xics.h"
static void powernv_cpu_reset(void *opaque)
{
@@ -110,23 +111,37 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, Error **errp)
+static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
{
Error *local_err = NULL;
CPUState *cs = CPU(child);
PowerPCCPU *cpu = POWERPC_CPU(cs);
+ Object *obj;
+
+ obj = object_new(TYPE_PNV_ICP);
+ object_property_add_child(OBJECT(cpu), "icp", obj, NULL);
+ object_property_add_const_link(obj, "xics", OBJECT(xi), &error_abort);
+ object_property_set_bool(obj, true, "realized", &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
object_property_set_bool(child, true, "realized", &local_err);
if (local_err) {
+ object_unparent(obj);
error_propagate(errp, local_err);
return;
}
powernv_cpu_init(cpu, &local_err);
if (local_err) {
+ object_unparent(obj);
error_propagate(errp, local_err);
return;
}
+
+ xics_cpu_setup(xi, cpu, ICP(obj));
}
static void pnv_core_realize(DeviceState *dev, Error **errp)
@@ -140,6 +155,14 @@ static void pnv_core_realize(DeviceState *dev, Error
**errp)
void *obj;
int i, j;
char name[32];
+ Object *xi;
+
+ xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
+ if (!xi) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(local_err));
+ return;
+ }
pc->threads = g_malloc0(size * cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
@@ -160,7 +183,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
for (j = 0; j < cc->nr_threads; j++) {
obj = pc->threads + j * size;
- pnv_core_realize_child(obj, &local_err);
+ pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
if (local_err) {
goto err;
}
--
2.9.3
- [Qemu-ppc] [PULL 00/48] ppc-for-2.10 queue 20170426, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 01/48] target/ppc: Improve accuracy of guest HTM availability on P8s, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 04/48] hw/ppc/pnv: Classify the "PowerNV Chip" devices as CPU devices, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 03/48] ppc/spapr: QOM'ify sPAPRRTCState, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 10/48] spapr: move spapr_populate_pa_features(), David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 02/48] pseries: Add pseries-2.10 machine type, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 08/48] target/ppc: Add new H-CALL shells for in memory table translation, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 11/48] spapr: Enable ISA 3.0 MMU mode selection via CAS, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 20/48] ppc/xics: add a realize() handler to ICPStateClass, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 21/48] ppc/pnv: add a PnvICPState object, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 24/48] ppc/pnv: create the ICP object under PnvCore,
David Gibson <=
- [Qemu-ppc] [PULL 06/48] spapr: Add ibm, processor-radix-AP-encodings to the device tree, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 12/48] spapr: Workaround for broken radix guests, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 17/48] ppc/xics: introduce an 'intc' backlink under PowerPCCPU, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 37/48] ppc/pnv: enable only one LPC bus, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 38/48] ppc/pnv: scan ISA bus to populate device tree, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 23/48] ppc/pnv: extend the machine with a InterruptStatsProvider interface, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 40/48] ppc/pnv: populate device tree for serial devices, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 28/48] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 45/48] target/ppc: Flush TLB on write to PIDR, David Gibson, 2017/04/26
- [Qemu-ppc] [PULL 07/48] target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3, David Gibson, 2017/04/26