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[Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbie to
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbie to check privilege level based on GTSE |
Date: |
Fri, 28 Apr 2017 16:58:23 +1000 |
The Guest Translation Shootdown Enable (GTSE) bit in the Logical Partition
Control Register (LPCR) can be set to enable a guest to use the tlbie
instruction directly to invalidate translations.
When the GTSE bit is set then the tlbie instruction is supervisor
privileged, otherwise it is hypervisor privileged.
Add a guest translation shootdown enable (gtse) field to the diassembly
context and use this to check the correct privilege level at code
generation time.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
---
V4 -> V5:
- Add to and use a field in the DisasContext so that we check at code gen
time rather than execution time
-> V4:
- Added patch to series
---
target/ppc/translate.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f40b5a1..e8aa83d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -214,6 +214,7 @@ struct DisasContext {
bool vsx_enabled;
bool spe_enabled;
bool tm_enabled;
+ bool gtse;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -4513,7 +4514,12 @@ static void gen_tlbie(DisasContext *ctx)
GEN_PRIV;
#else
TCGv_i32 t1;
- CHK_HV;
+
+ if (ctx->gtse) {
+ CHK_SV; /* If gtse is set then tblie is supervisor privileged */
+ } else {
+ CHK_HV; /* Else hypervisor privileged */
+ }
if (NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new();
@@ -7227,6 +7233,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
TranslationBlock *tb)
ctx.tm_enabled = false;
}
#endif
+ ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
--
2.5.5
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 0/6] target/ppc: Implement POWER9 pseries TCG RADIX Support, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 2/6] target/ppc: Flush TLB on write to PIDR, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 3/6] target/ppc: Update tlbie to check privilege level based on GTSE,
Suraj Jitindar Singh <=
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 1/6] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 4/6] target/ppc: Change tlbie invalid fields for POWER9 support, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 5/6] target/ppc: Implement ISA V3.00 radix page fault handler, Suraj Jitindar Singh, 2017/04/28
- [Qemu-ppc] [QEMU-ppc for-2.10][PATCH V5 6/6] target/ppc: Enable RADIX mmu mode for pseries TCG guest, Suraj Jitindar Singh, 2017/04/28