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[Qemu-ppc] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs |
Date: |
Thu, 11 May 2017 14:14:12 +1000 |
From: Sam Bobroff <address@hidden>
Kernel commit 17d48610ae0f ("KVM: PPC: Book 3S: XICS: Implement ICS
P/Q states") added new bits to the state used by KVM IRQs. Currently,
QEMU does not preserve these bits, so migrating (or otherwise saving
and restoring) the guest state causes the P and Q bits to be cleared.
Clearing the P bit has no effect, because the kernel will set it based
on other data, but the loss of a set Q bit will cause a lost
interrupt.
This patch preserves the P and Q bits, correcting the problem.
Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xics_kvm.c | 12 ++++++++++++
include/hw/ppc/xics.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 03c1fc7..dd93531 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -229,6 +229,12 @@ static void ics_get_kvm_state(ICSState *ics)
| XICS_STATUS_REJECTED;
}
}
+ if (state & KVM_XICS_PRESENTED) {
+ irq->status |= XICS_STATUS_PRESENTED;
+ }
+ if (state & KVM_XICS_QUEUED) {
+ irq->status |= XICS_STATUS_QUEUED;
+ }
}
}
@@ -266,6 +272,12 @@ static int ics_set_kvm_state(ICSState *ics, int version_id)
state |= KVM_XICS_PENDING;
}
}
+ if (irq->status & XICS_STATUS_PRESENTED) {
+ state |= KVM_XICS_PRESENTED;
+ }
+ if (irq->status & XICS_STATUS_QUEUED) {
+ state |= KVM_XICS_QUEUED;
+ }
ret = ioctl(kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
if (ret != 0) {
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index c215dc7..68525c8 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -144,6 +144,8 @@ struct ICSIRQState {
#define XICS_STATUS_SENT 0x2
#define XICS_STATUS_REJECTED 0x4
#define XICS_STATUS_MASKED_PENDING 0x8
+#define XICS_STATUS_PRESENTED 0x10
+#define XICS_STATUS_QUEUED 0x20
uint8_t status;
/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
#define XICS_FLAGS_IRQ_LSI 0x1
--
2.9.3
- [Qemu-ppc] [PULL 00/23] ppc-for-2.10 queue 20170511, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 04/23] target/ppc: Generate fence operations, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 03/23] cputlb: handle first atomic write to the page, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 19/23] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 05/23] cpus: Fix CPU unplug for MTTCG, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs,
David Gibson <=
- [Qemu-ppc] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 10/23] Add QemuMacDrivers as submodule, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 21/23] target/ppc: Allow workarounds for POWER9 DD1, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 14/23] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 17/23] target/ppc: Implement ISA V3.00 radix page fault handler, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 16/23] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/11
- [Qemu-ppc] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/11