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Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POW
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9 |
Date: |
Mon, 10 Jul 2017 20:26:55 +1000 |
User-agent: |
Mutt/1.8.3 (2017-05-23) |
On Wed, Jul 05, 2017 at 07:13:16PM +0200, Cédric Le Goater wrote:
> Prepare ground for the new exception model XIVE of POWER9.
I'm a bit confused by this. The excp_model is about the CPU core's
irq model, not the external irq controller's.
Now.. I could imagine the POWER9 having a different core model that
came along with XIVE, but I can't see this new model being used for
anything anywhere in the rest of the series.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
> ---
> target/ppc/cpu-qom.h | 2 ++
> target/ppc/excp_helper.c | 9 ++++++---
> target/ppc/translate.c | 3 ++-
> target/ppc/translate_init.c | 2 +-
> 4 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index d0cf6ca2a971..d7b78cf3f71c 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -132,6 +132,8 @@ enum powerpc_excp_t {
> POWERPC_EXCP_POWER7,
> /* POWER8 exception model */
> POWERPC_EXCP_POWER8,
> + /* POWER9 exception model */
> + POWERPC_EXCP_POWER9,
> };
>
>
> /*****************************************************************************/
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 3a9f0861e773..dc7dff36a580 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -148,9 +148,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> */
> #if defined(TARGET_PPC64)
> if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8) {
> + excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9) {
> lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - if (excp_model == POWERPC_EXCP_POWER8) {
> + if (excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9) {
> ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
> } else {
> ail = 0;
> @@ -651,7 +653,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
> new_msr |= (target_ulong)1 << MSR_LE;
> }
> - } else if (excp_model == POWERPC_EXCP_POWER8) {
> + } else if (excp_model == POWERPC_EXCP_POWER8 ||
> + excp_model == POWERPC_EXCP_POWER9) {
> if (new_msr & MSR_HVB) {
> if (env->spr[SPR_HID0] & HID0_HILE) {
> new_msr |= (target_ulong)1 << MSR_LE;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index c0cd64d927c2..2d8c1b9e6836 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -7064,7 +7064,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
> fprintf_function cpu_fprintf,
>
> #if defined(TARGET_PPC64)
> if (env->excp_model == POWERPC_EXCP_POWER7 ||
> - env->excp_model == POWERPC_EXCP_POWER8) {
> + env->excp_model == POWERPC_EXCP_POWER8 ||
> + env->excp_model == POWERPC_EXCP_POWER9) {
> cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
> env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
> }
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 53aff5a7b734..b8c7b8150318 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8962,7 +8962,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> pcc->sps = &POWER7_POWER8_sps;
> pcc->radix_page_info = &POWER9_radix_page_info;
> #endif
> - pcc->excp_model = POWERPC_EXCP_POWER8;
> + pcc->excp_model = POWERPC_EXCP_POWER9;
> pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
> pcc->bfd_mach = bfd_mach_ppc64;
> pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [RFC PATCH 00/26] guest exploitation of the XIVE interrupt controller (POWER9), Cédric Le Goater, 2017/07/05
- [Qemu-ppc] [RFC PATCH 02/26] spapr: populate device tree depending on XIVE_EXPLOIT option, Cédric Le Goater, 2017/07/05
- [Qemu-ppc] [RFC PATCH 01/26] spapr: introduce the XIVE_EXPLOIT option in CAS, Cédric Le Goater, 2017/07/05
- [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Cédric Le Goater, 2017/07/05
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9,
David Gibson <=
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Cédric Le Goater, 2017/07/10
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Benjamin Herrenschmidt, 2017/07/10
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Cédric Le Goater, 2017/07/11
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, David Gibson, 2017/07/11
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Cédric Le Goater, 2017/07/11
- Re: [Qemu-ppc] [RFC PATCH 03/26] target/ppc/POWER9: add POWERPC_EXCP_POWER9, Benjamin Herrenschmidt, 2017/07/11
[Qemu-ppc] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model, Cédric Le Goater, 2017/07/05