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[Qemu-ppc] [PULL 26/34] ppc: pnv: use generic cpu_model parsing
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 26/34] ppc: pnv: use generic cpu_model parsing |
Date: |
Tue, 17 Oct 2017 15:21:44 +1100 |
From: Igor Mammedov <address@hidden>
use common cpu_model prasing in vl.c and set default cpu_model
using generic MachineClass::default_cpu_type.
Beside of switching to generic infrastructure it solves several
issues.
* ppc_cpu_class_by_name() is used to deal with lower/upper case
and alias translations into actual cpu type, which fixes
'-M powernv -cpu power8' and '-M powernv -cpu power9_v1.0'
usecases which error out with:
'invalid CPU model 'FOO' for powernv machine'
* allows to switch to lower-case typenames in pnv chip/core name
(by convention typnames should be lower-case)
* replace aliased names /power8, power9, .../ with exact cpu model
names (i.e. typenames should be stable but aliases might decide to
point to other cpu model withi family or changed by kvm). It will
also help to simplify pnv_chip/core code and get rid of dependency
on cpu_model parsing.
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Updated to make DD2.0 as default POWER9 chip]
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 22 ++++++++++------------
hw/ppc/pnv_core.c | 2 +-
include/hw/ppc/pnv.h | 8 ++++----
3 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 84b2389ea6..a2cb4a40ff 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -606,16 +606,13 @@ static void ppc_powernv_init(MachineState *machine)
}
}
- /* We need some cpu model to instantiate the PnvChip class */
- if (machine->cpu_model == NULL) {
- machine->cpu_model = "POWER8";
- }
-
/* Create the processor chips */
- chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
+ i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
+ chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%.*s",
+ i, machine->cpu_type);
if (!object_class_by_name(chip_typename)) {
- error_report("invalid CPU model '%s' for %s machine",
- machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
+ error_report("invalid CPU model '%.*s' for %s machine",
+ i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name);
exit(1);
}
@@ -715,7 +712,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass,
void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->cpu_model = "POWER8E";
+ k->cpu_model = "power8e_v2.1";
k->chip_type = PNV_CHIP_POWER8E;
k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
@@ -737,7 +734,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass,
void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->cpu_model = "POWER8";
+ k->cpu_model = "power8_v2.0";
k->chip_type = PNV_CHIP_POWER8;
k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
@@ -759,7 +756,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
*klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->cpu_model = "POWER8NVL";
+ k->cpu_model = "power8nvl_v1.0";
k->chip_type = PNV_CHIP_POWER8NVL;
k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
@@ -781,7 +778,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass,
void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PnvChipClass *k = PNV_CHIP_CLASS(klass);
- k->cpu_model = "POWER9";
+ k->cpu_model = "power9_v2.0";
k->chip_type = PNV_CHIP_POWER9;
k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
k->cores_mask = POWER9_CORE_MASK;
@@ -1132,6 +1129,7 @@ static void powernv_machine_class_init(ObjectClass *oc,
void *data)
mc->init = ppc_powernv_init;
mc->reset = ppc_powernv_reset;
mc->max_cpus = MAX_CPUS;
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
* storage */
mc->no_parallel = 1;
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 67264830db..91f02cb324 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -227,7 +227,7 @@ static const TypeInfo pnv_core_info = {
};
static const char *pnv_core_models[] = {
- "POWER8E", "POWER8", "POWER8NVL", "POWER9"
+ "power8e_v2.1", "power8_v2.0", "power8nvl_v1.0", "power9_v2.0"
};
static void pnv_core_register_types(void)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 9c5437dabc..d80fa44bf0 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -80,19 +80,19 @@ typedef struct PnvChipClass {
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
} PnvChipClass;
-#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
+#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-power8e_v2.1"
#define PNV_CHIP_POWER8E(obj) \
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
-#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8"
+#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-power8_v2.0"
#define PNV_CHIP_POWER8(obj) \
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
-#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL"
+#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-power8nvl_v1.0"
#define PNV_CHIP_POWER8NVL(obj) \
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
-#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9"
+#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-power9_v2.0"
#define PNV_CHIP_POWER9(obj) \
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
--
2.13.6
- [Qemu-ppc] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user, (continued)
- [Qemu-ppc] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 23/34] ppc: spapr: use cpu model names as tcg defaults instead of aliases, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 34/34] spapr_cpu_core: rewrite machine type sanity check, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 28/34] ppc: pnv: drop PnvCoreClass::cpu_oc field, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 29/34] ppc: pnv: define core types statically, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 21/34] ppc: spapr: use cpu type name directly, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 20/34] ppc: spapr: define core types statically, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 17/34] ppc: 40p/prep: replace cpu_model with cpu_type, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 30/34] ppc: pnv: drop PnvChipClass::cpu_model field, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 32/34] spapr: Correct RAM size calculation for HPT resizing, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 26/34] ppc: pnv: use generic cpu_model parsing,
David Gibson <=
- [Qemu-ppc] [PULL 27/34] ppc: pnv: normalize core/chip type names, David Gibson, 2017/10/17
- [Qemu-ppc] [PULL 25/34] ppc: spapr: use generic cpu_model parsing, David Gibson, 2017/10/17
- Re: [Qemu-ppc] [PULL 00/34] ppc-for-2.11 queue 20171017, Peter Maydell, 2017/10/19