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[Qemu-ppc] [PULL 17/35] target/ppc: Split out gen_load_locked
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 17/35] target/ppc: Split out gen_load_locked |
Date: |
Tue, 3 Jul 2018 15:57:46 +1000 |
From: Richard Henderson <address@hidden>
Leave only the minimal amount of code within the LDAR macro,
moving the rest of the code into gen_load_locked. Use MO_ALIGN
and remove the explicit call to gen_check_align.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e751072404..f48fcbeefb 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3070,23 +3070,24 @@ static void gen_isync(DisasContext *ctx)
#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
-#define LARX(name, memop) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv t0; \
- TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
- int len = MEMOP_GET_SIZE(memop); \
- gen_set_access_type(ctx, ACCESS_RES); \
- t0 = tcg_temp_local_new(); \
- gen_addr_reg_index(ctx, t0); \
- if ((len) > 1) { \
- gen_check_align(ctx, t0, (len)-1); \
- } \
- tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
- tcg_gen_mov_tl(cpu_reserve, t0); \
- tcg_gen_mov_tl(cpu_reserve_val, gpr); \
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
- tcg_temp_free(t0); \
+static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
+{
+ TCGv gpr = cpu_gpr[rD(ctx->opcode)];
+ TCGv t0 = tcg_temp_new();
+
+ gen_set_access_type(ctx, ACCESS_RES);
+ gen_addr_reg_index(ctx, t0);
+ tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
+ tcg_gen_mov_tl(cpu_reserve, t0);
+ tcg_gen_mov_tl(cpu_reserve_val, gpr);
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ tcg_temp_free(t0);
+}
+
+#define LARX(name, memop) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ gen_load_locked(ctx, memop); \
}
/* lwarx */
--
2.17.1
- Re: [Qemu-ppc] [Qemu-devel] [PULL 35/35] ppc: Include vga cirrus card into the compiling process, (continued)
- [Qemu-ppc] [PULL 23/35] target/ppc: Implement the rest of gen_st_atomic, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 08/35] ppc/xics: move the vmstate structures under the ics-base class, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 04/35] ppc/xics: introduce ICP DeviceRealize and DeviceReset handlers, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 05/35] ppc/xics: introduce a parent_realize in ICSStateClass, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 32/35] spapr: compute default value of "hpt-max-page-size" later, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 21/35] target/ppc: Use atomic min/max helpers, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 26/35] ppc4xx_i2c: Rewrite to model hardware more closely, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 14/35] target/ppc: Use atomic cmpxchg for STQCX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 17/35] target/ppc: Split out gen_load_locked,
David Gibson <=
- [Qemu-ppc] [PULL 13/35] target/ppc: Use atomic store for STQ, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 25/35] hw/ppc: Give sam46ex its own config option, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 18/35] target/ppc: Split out gen_ld_atomic, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 12/35] target/ppc: Use atomic load for LQ and LQARX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 31/35] target/ppc/kvm: don't pass cpu to kvm_get_smmu_info(), David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 15/35] target/ppc: Remove POWERPC_EXCP_STCX, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 29/35] ppc440_uc: Basic emulation of PPC440 DMA controller, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 24/35] fpu_helper.c: fix setting FPSCR[FI] bit, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 34/35] target/ppc: Relax reserved bitmask of indexed store instructions, David Gibson, 2018/07/03
- [Qemu-ppc] [PULL 30/35] target/ppc/kvm: get rid of kvm_get_fallback_smmu_info(), David Gibson, 2018/07/03