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[Qemu-ppc] [PATCH 22/34] target/ppc: convert VSX logical operations to v
From: |
Richard Henderson |
Subject: |
[Qemu-ppc] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations |
Date: |
Mon, 17 Dec 2018 22:38:59 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 43 ++++++++++++-----------------
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 1608ad48b1..8ab1290026 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -10,6 +10,11 @@ static inline void set_vsr(int n, TCGv_i64 src)
tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1]));
}
+static inline int vsr_full_offset(int n)
+{
+ return offsetof(CPUPPCState, vsr[n].u64[0]);
+}
+
static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
{
if (n < 32) {
@@ -1214,40 +1219,26 @@ static void gen_xxbrw(DisasContext *ctx)
tcg_temp_free_i64(xbl);
}
-#define VSX_LOGICAL(name, tcg_op) \
+#define VSX_LOGICAL(name, vece, tcg_op) \
static void glue(gen_, name)(DisasContext * ctx) \
{ \
- TCGv_i64 t0; \
- TCGv_i64 t1; \
- TCGv_i64 t2; \
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- t0 = tcg_temp_new_i64(); \
- t1 = tcg_temp_new_i64(); \
- t2 = tcg_temp_new_i64(); \
- get_cpu_vsrh(t0, xA(ctx->opcode)); \
- get_cpu_vsrh(t1, xB(ctx->opcode)); \
- tcg_op(t2, t0, t1); \
- set_cpu_vsrh(xT(ctx->opcode), t2); \
- get_cpu_vsrl(t0, xA(ctx->opcode)); \
- get_cpu_vsrl(t1, xB(ctx->opcode)); \
- tcg_op(t2, t0, t1); \
- set_cpu_vsrl(xT(ctx->opcode), t2); \
- tcg_temp_free_i64(t0); \
- tcg_temp_free_i64(t1); \
- tcg_temp_free_i64(t2); \
+ tcg_op(vece, vsr_full_offset(xT(ctx->opcode)), \
+ vsr_full_offset(xA(ctx->opcode)), \
+ vsr_full_offset(xB(ctx->opcode)), 16, 16); \
}
-VSX_LOGICAL(xxland, tcg_gen_and_i64)
-VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
-VSX_LOGICAL(xxlor, tcg_gen_or_i64)
-VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
-VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
-VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
-VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
-VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
+VSX_LOGICAL(xxland, MO_64, tcg_gen_gvec_and)
+VSX_LOGICAL(xxlandc, MO_64, tcg_gen_gvec_andc)
+VSX_LOGICAL(xxlor, MO_64, tcg_gen_gvec_or)
+VSX_LOGICAL(xxlxor, MO_64, tcg_gen_gvec_xor)
+VSX_LOGICAL(xxlnor, MO_64, tcg_gen_gvec_nor)
+VSX_LOGICAL(xxleqv, MO_64, tcg_gen_gvec_eqv)
+VSX_LOGICAL(xxlnand, MO_64, tcg_gen_gvec_nand)
+VSX_LOGICAL(xxlorc, MO_64, tcg_gen_gvec_orc)
#define VSX_XXMRG(name, high) \
static void glue(gen_, name)(DisasContext * ctx) \
--
2.17.2
- Re: [Qemu-ppc] [PATCH 25/34] target/ppc: convert xxsel to vector operations, (continued)
- [Qemu-ppc] [PATCH 15/34] target/ppc: merge ppc_vsr_t and ppc_avr_t union types, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 06/34] tcg/i386: Implement vector saturating arithmetic, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 18/34] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations,
Richard Henderson <=
- [Qemu-ppc] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 31/34] target/ppc: Add set_vscr_sat, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 21/34] target/ppc: nand, nor, eqv are now generic vector operations, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 04/34] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2018/12/18
- [Qemu-ppc] [PATCH 20/34] target/ppc: convert vsplt[bhw] to use vector operations, Richard Henderson, 2018/12/18