[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 15/43] spapr/irq: add an 'nr_irq' parameter to initiali
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 15/43] spapr/irq: add an 'nr_irq' parameter to initialize the backend. |
Date: |
Tue, 19 Feb 2019 01:30:21 +1100 |
From: Cédric Le Goater <address@hidden>
When using the 'dual' interrupt mode, the source numbers of both sPAPR
IRQ backends are aligned to share a common IRQ number space and to use
a similar mapping of the machine qemu_irq array which is indexed by
the source number.
The XICS IRQ number range initially being [ 0x1000 - 0x2000 ], this
requires to change the XICS ICSState offset to 0 and to provision for
an extra 4K of source numbers and qemu_irqs which will never be used
by the machine when running under the XICS interrupt mode. This is not
an optimal solution.
Change the init() method to allocate an IRQ number space of the
expected size for the XICS sPAPR IRQ backend. It breaks the interrupt
signaling when under the 'dual' mode because source numbers have
unexpected values but next patch will fix that.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_irq.c | 18 ++++++++++--------
include/hw/ppc/spapr_irq.h | 2 +-
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 80b0083b8e..da52a46e80 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -93,10 +93,10 @@ error:
return NULL;
}
-static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_xics(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
- int nr_irqs = spapr->irq->nr_irqs;
Error *local_err = NULL;
if (kvm_enabled()) {
@@ -262,7 +262,8 @@ sPAPRIrq spapr_irq_xics = {
/*
* XIVE IRQ backend.
*/
-static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_xive(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
uint32_t nr_servers = spapr_max_server_number(spapr);
@@ -278,7 +279,7 @@ static void spapr_irq_init_xive(sPAPRMachineState *spapr,
Error **errp)
}
dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
- qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
+ qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
/*
* 8 XIVE END structures per CPU. One for each available priority
*/
@@ -435,7 +436,8 @@ static sPAPRIrq *spapr_irq_current(sPAPRMachineState *spapr)
&spapr_irq_xive : &spapr_irq_xics;
}
-static void spapr_irq_init_dual(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_dual(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
Error *local_err = NULL;
@@ -445,7 +447,7 @@ static void spapr_irq_init_dual(sPAPRMachineState *spapr,
Error **errp)
return;
}
- spapr_irq_xics.init(spapr, &local_err);
+ spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -462,7 +464,7 @@ static void spapr_irq_init_dual(sPAPRMachineState *spapr,
Error **errp)
*/
spapr->ics->offset = 0;
- spapr_irq_xive.init(spapr, &local_err);
+ spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -618,7 +620,7 @@ void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
}
- spapr->irq->init(spapr, errp);
+ spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
spapr->irq->nr_irqs);
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 14b02c3aca..488511c3d8 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -35,7 +35,7 @@ typedef struct sPAPRIrq {
uint32_t nr_msis;
uint8_t ov5;
- void (*init)(sPAPRMachineState *spapr, Error **errp);
+ void (*init)(sPAPRMachineState *spapr, int nr_irqs, Error **errp);
int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
void (*free)(sPAPRMachineState *spapr, int irq, int num);
qemu_irq (*qirq)(sPAPRMachineState *spapr, int irq);
--
2.20.1
- [Qemu-ppc] [PULL 03/43] target/ppc: Enable reporting of SPRs to GDB, (continued)
- [Qemu-ppc] [PULL 03/43] target/ppc: Enable reporting of SPRs to GDB, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 06/43] cuda: decrease time delay before raising VIA SR interrupt and remove fast path, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 10/43] ppc: fix crash during branch stepping, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 09/43] target/ppc: Remove some #if 0'ed code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 11/43] xive: Only set source type for LSIs, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 13/43] target/ppc: Disable ISA 2.06 PM instructions on POWER9, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 16/43] spapr/irq: remove the XICS offset adjustment, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 17/43] xics: Explicitely call KVM ICP methods from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 19/43] xics: Handle KVM ICP realize from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 12/43] qdev: pass an Object * to qbus_set_hotplug_handler(), David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 15/43] spapr/irq: add an 'nr_irq' parameter to initialize the backend.,
David Gibson <=
- [Qemu-ppc] [PULL 14/43] spapr: fix out of bounds write in spapr_populate_drmem_v2, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 23/43] xics: Handle KVM ICS reset from the "simple" ICS code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 18/43] xics: Handle KVM ICP reset from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 22/43] xics: Explicitely call KVM ICS methods from the common code, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 27/43] target/ppc: convert VMX logical instructions to use vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 21/43] xics: Drop the KVM ICP class, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 20/43] spapr/irq: Use the base ICP class for KVM, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 31/43] target/ppc: convert VSX logical operations to vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 25/43] spapr/irq: Use the "simple" ICS class for KVM, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 29/43] target/ppc: convert vspltis[bhw] to use vector operations, David Gibson, 2019/02/18