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[Qemu-ppc] [PULL 34/43] target/ppc: convert xxsel to vector operations
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 34/43] target/ppc: convert xxsel to vector operations |
Date: |
Tue, 19 Feb 2019 01:30:40 +1100 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Acked-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 55 ++++++++++++++---------------
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 0e8cecb00a..e73197e717 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1321,40 +1321,39 @@ static void glue(gen_, name)(DisasContext * ctx)
\
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
-static void gen_xxsel(DisasContext * ctx)
+static void xxsel_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
{
- TCGv_i64 a, b, c, tmp;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- a = tcg_temp_new_i64();
- b = tcg_temp_new_i64();
- c = tcg_temp_new_i64();
- tmp = tcg_temp_new_i64();
-
- get_cpu_vsrh(a, xA(ctx->opcode));
- get_cpu_vsrh(b, xB(ctx->opcode));
- get_cpu_vsrh(c, xC(ctx->opcode));
-
tcg_gen_and_i64(b, b, c);
tcg_gen_andc_i64(a, a, c);
- tcg_gen_or_i64(tmp, a, b);
- set_cpu_vsrh(xT(ctx->opcode), tmp);
+ tcg_gen_or_i64(t, a, b);
+}
- get_cpu_vsrl(a, xA(ctx->opcode));
- get_cpu_vsrl(b, xB(ctx->opcode));
- get_cpu_vsrl(c, xC(ctx->opcode));
+static void xxsel_vec(unsigned vece, TCGv_vec t, TCGv_vec a,
+ TCGv_vec b, TCGv_vec c)
+{
+ tcg_gen_and_vec(vece, b, b, c);
+ tcg_gen_andc_vec(vece, a, a, c);
+ tcg_gen_or_vec(vece, t, a, b);
+}
- tcg_gen_and_i64(b, b, c);
- tcg_gen_andc_i64(a, a, c);
- tcg_gen_or_i64(tmp, a, b);
- set_cpu_vsrl(xT(ctx->opcode), tmp);
+static void gen_xxsel(DisasContext *ctx)
+{
+ static const GVecGen4 g = {
+ .fni8 = xxsel_i64,
+ .fniv = xxsel_vec,
+ .vece = MO_64,
+ };
+ int rt = xT(ctx->opcode);
+ int ra = xA(ctx->opcode);
+ int rb = xB(ctx->opcode);
+ int rc = xC(ctx->opcode);
- tcg_temp_free_i64(a);
- tcg_temp_free_i64(b);
- tcg_temp_free_i64(c);
- tcg_temp_free_i64(tmp);
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_gvec_4(vsr_full_offset(rt), vsr_full_offset(ra),
+ vsr_full_offset(rb), vsr_full_offset(rc), 16, 16, &g);
}
static void gen_xxspltw(DisasContext *ctx)
--
2.20.1
- [Qemu-ppc] [PULL 33/43] target/ppc: convert xxspltw to vector operations, (continued)
- [Qemu-ppc] [PULL 33/43] target/ppc: convert xxspltw to vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 39/43] target/ppc: Use mtvscr/mfvscr for vmstate, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 30/43] target/ppc: convert vsplt[bhw] to use vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 32/43] target/ppc: convert xxspltib to vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 37/43] target/ppc: Remove vscr_nj and vscr_sat, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 41/43] target/ppc: Split out VSCR_SAT to a vector field, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 40/43] target/ppc: Add set_vscr_sat, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 43/43] target/ppc: convert vmin* and vmax* to vector operations, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 35/43] target/ppc: Pass integer to helper_mtvscr, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 38/43] target/ppc: Add helper_mfvscr, David Gibson, 2019/02/18
- [Qemu-ppc] [PULL 34/43] target/ppc: convert xxsel to vector operations,
David Gibson <=
- [Qemu-ppc] [PULL 42/43] target/ppc: convert vadd*s and vsub*s to vector operations, David Gibson, 2019/02/18
- Re: [Qemu-ppc] [PULL 00/43] ppc-for-4.0 queue 20190219, Peter Maydell, 2019/02/19