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[Qemu-ppc] [PULL 03/50] target/ppc: Fix support for "STOP light" states
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 03/50] target/ppc: Fix support for "STOP light" states on POWER9 |
Date: |
Tue, 26 Feb 2019 15:52:17 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
STOP must act differently based on PSSCR:EC on POWER9. When set, it
acts like the P7/P8 power management instructions and wake up at 0x100
based on the wakeup conditions in LPCR.
When PSSCR:EC is clear however it will wakeup at the next instruction
after STOP (if EE is clear) or take the corresponding interrupts (if
EE is set).
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu-qom.h | 1 +
target/ppc/cpu.h | 12 +++++++++---
target/ppc/excp_helper.c | 8 ++++++--
target/ppc/translate.c | 13 ++++++++++++-
target/ppc/translate_init.inc.c | 7 +++++++
5 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 3130802304..e9cb158423 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -122,6 +122,7 @@ typedef enum {
PPC_PM_NAP,
PPC_PM_SLEEP,
PPC_PM_RVWINKLE,
+ PPC_PM_STOP,
} powerpc_pm_insn_t;
/*****************************************************************************/
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 325ebbeb98..5b1899bfc9 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -414,6 +414,10 @@ struct ppc_slb_t {
#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
#define LPCR_HDICE PPC_BIT(63)
+/* PSSCR bits */
+#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
+#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
+
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
#define msr_shv ((env->msr >> MSR_SHV) & 1)
@@ -1110,9 +1114,11 @@ struct CPUPPCState {
* instructions and SPRs are diallowed if MSR:HV is 0
*/
bool has_hv_mode;
- /* On P7/P8, set when in PM state, we need to handle resume
- * in a special way (such as routing some resume causes to
- * 0x100), so flag this here.
+
+ /*
+ * On P7/P8/P9, set when in PM state, we need to handle resume in
+ * a special way (such as routing some resume causes to 0x100), so
+ * flag this here.
*/
bool in_pm_state;
#endif
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7c7c8d1b9d..97503193ef 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -97,7 +97,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
asrr0 = -1;
asrr1 = -1;
- /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
+ /*
+ * check for special resume at 0x100 from doze/nap/sleep/winkle on
+ * P7/P8/P9
+ */
if (env->in_pm_state) {
env->in_pm_state = false;
@@ -960,7 +963,8 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
/* Condition for waking up at 0x100 */
- env->in_pm_state = true;
+ env->in_pm_state = (insn != PPC_PM_STOP) ||
+ (env->spr[SPR_PSSCR] & PSSCR_EC);
}
#endif /* defined(TARGET_PPC64) */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index bffdbd9687..fde7ead7b7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3589,7 +3589,18 @@ static void gen_nap(DisasContext *ctx)
static void gen_stop(DisasContext *ctx)
{
- gen_nap(ctx);
+#if defined(CONFIG_USER_ONLY)
+ GEN_PRIV;
+#else
+ TCGv_i32 t;
+
+ CHK_HV;
+ t = tcg_const_i32(PPC_PM_STOP);
+ gen_helper_pminsn(cpu_env, t);
+ tcg_temp_free_i32(t);
+ /* Stop translation, as the CPU is supposed to sleep from now */
+ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+#endif /* defined(CONFIG_USER_ONLY) */
}
static void gen_sleep(DisasContext *ctx)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index d884906004..8b1d324b3b 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8801,9 +8801,16 @@ static bool cpu_has_work_POWER9(CPUState *cs)
CPUPPCState *env = &cpu->env;
if (cs->halted) {
+ uint64_t psscr = env->spr[SPR_PSSCR];
+
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
return false;
}
+
+ /* If EC is clear, just return true on any pending interrupt */
+ if (!(psscr & PSSCR_EC)) {
+ return true;
+ }
/* External Exception */
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
--
2.20.1
- [Qemu-ppc] [PULL 00/50] ppc-for-4.0 queue 20190226, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 01/50] target/ppc: Fix nip on power management instructions, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 04/50] target/ppc: Move "wakeup reset" code to a separate function, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 02/50] target/ppc: Don't clobber MSR:EE on PM instructions, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 03/50] target/ppc: Fix support for "STOP light" states on POWER9,
David Gibson <=
- [Qemu-ppc] [PULL 13/50] spapr: support memory unplug for qtest, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 10/50] target/ppc: Add support for LPCR:HEIC on POWER9, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 05/50] target/ppc: Rename "in_pm_state" to "resume_as_sreset", David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 11/50] ppc: add host-serial and host-model machine attributes (CVE-2019-8934), David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 08/50] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 09/50] target/ppc: Add POWER9 external interrupt model, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 21/50] target/ppc: Fix #include guard in mmu-book3s-v3.h, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 20/50] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 07/50] target/ppc: Detect erroneous condition in interrupt delivery, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 19/50] target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translation, David Gibson, 2019/02/25