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[Qemu-ppc] [PULL 06/50] target/ppc: Add POWER9 exception model
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 06/50] target/ppc: Add POWER9 exception model |
Date: |
Tue, 26 Feb 2019 15:52:20 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
And use it to get the correct HILE bit in HID0
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu-qom.h | 2 ++
target/ppc/excp_helper.c | 17 +++++++++++++----
target/ppc/translate.c | 3 ++-
target/ppc/translate_init.inc.c | 2 +-
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index e9cb158423..904ee694ac 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -113,6 +113,8 @@ enum powerpc_excp_t {
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
+ /* POWER9 exception model */
+ POWERPC_EXCP_POWER9,
};
/*****************************************************************************/
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7536620a41..37546bb0f0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -147,7 +147,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
/* Exception targetting modifiers
*
- * LPES0 is supported on POWER7/8
+ * LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
*
* On anything else, we behave as if LPES0 is 1
@@ -158,9 +158,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
*/
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8) {
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9) {
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- if (excp_model == POWERPC_EXCP_POWER8) {
+ if (excp_model != POWERPC_EXCP_POWER7) {
ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
} else {
ail = 0;
@@ -662,7 +663,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
} else if (excp_model == POWERPC_EXCP_POWER8) {
if (new_msr & MSR_HVB) {
- if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) {
+ if (env->spr[SPR_HID0] & HID0_HILE) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+ } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+ } else if (excp_model == POWERPC_EXCP_POWER9) {
+ if (new_msr & MSR_HVB) {
+ if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
new_msr |= (target_ulong)1 << MSR_LE;
}
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index fde7ead7b7..819221f246 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7481,7 +7481,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
#if defined(TARGET_PPC64)
if (env->excp_model == POWERPC_EXCP_POWER7 ||
- env->excp_model == POWERPC_EXCP_POWER8) {
+ env->excp_model == POWERPC_EXCP_POWER8 ||
+ env->excp_model == POWERPC_EXCP_POWER9) {
cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 8b1d324b3b..9909e58761 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8905,7 +8905,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
pcc->radix_page_info = &POWER9_radix_page_info;
#endif
- pcc->excp_model = POWERPC_EXCP_POWER8;
+ pcc->excp_model = POWERPC_EXCP_POWER9;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
pcc->bfd_mach = bfd_mach_ppc64;
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
--
2.20.1
- [Qemu-ppc] [PULL 05/50] target/ppc: Rename "in_pm_state" to "resume_as_sreset", (continued)
- [Qemu-ppc] [PULL 05/50] target/ppc: Rename "in_pm_state" to "resume_as_sreset", David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 11/50] ppc: add host-serial and host-model machine attributes (CVE-2019-8934), David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 08/50] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 09/50] target/ppc: Add POWER9 external interrupt model, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 21/50] target/ppc: Fix #include guard in mmu-book3s-v3.h, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 20/50] target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 07/50] target/ppc: Detect erroneous condition in interrupt delivery, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 19/50] target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translation, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 18/50] target/ppc/spapr: Set LPCR:HR when using Radix mode, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 31/50] spapr: Generate FDT fragment for CPUs at configure connector time, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 06/50] target/ppc: Add POWER9 exception model,
David Gibson <=
- [Qemu-ppc] [PULL 12/50] cpus: Properly release the iothread lock when killing a dummy VCPU, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 15/50] tests/device-plug: Add CCW unplug test for s390x, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 17/50] tests/device-plug: Add memory unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 16/50] tests/device-plug: Add CPU core unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 24/50] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 26/50] target/ppc: Rename PATB/PATBE -> PATE, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 14/50] tests/device-plug: Add a simple PCI unplug request test, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 25/50] target/ppc: Flush the TLB locally when the LPIDR is written, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 23/50] target/ppc: Add basic support for "new format" HPTE as found on POWER9, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 22/50] target/ppc: Fix ordering of hash MMU accesses, David Gibson, 2019/02/25