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Re: [Qemu-ppc] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro |
Date: |
Thu, 7 Mar 2019 14:30:53 +1100 |
User-agent: |
Mutt/1.11.3 (2019-02-01) |
On Wed, Mar 06, 2019 at 09:50:17AM +0100, Cédric Le Goater wrote:
> This is a simple helper to translate XSCOM addresses to MMIO addresses
>
> Signed-off-by: Cédric Le Goater <address@hidden>
A worthy cleanup, regardless of anything else. Applied.
> ---
> hw/ppc/pnv_psi.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index c872be0b9c0d..a2f8d0dece80 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -114,6 +114,8 @@
> #define PSIHB_BAR_MASK 0x0003fffffff00000ull
> #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull
>
> +#define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
> +
> static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
> {
> MemoryRegion *sysmem = get_system_memory();
> @@ -392,13 +394,13 @@ static void pnv_psi_reg_write(PnvPsi *psi, uint32_t
> offset, uint64_t val,
> */
> static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
> {
> - return pnv_psi_reg_read(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, true);
> + return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
> }
>
> static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> - pnv_psi_reg_write(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, val, true);
> + pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
> }
>
> static const MemoryRegionOps psi_mmio_ops = {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 00/27] ppc: add POWER9 support to the PowerNV platform, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 04/27] ppc/pnv: export the xive_router_notify() routine, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 03/27] ppc/xive: export the TIMA memory accessors, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 07/27] ppc/pnv: introduce a new dt_populate() operation to the chip model, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 11/27] ppc/pnv: fix logging primitives using Ox, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 02/27] ppc: externalize ppc_get_vcpu_by_pir(), Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro, Cédric Le Goater, 2019/03/06
- Re: [Qemu-ppc] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro,
David Gibson <=
- [Qemu-ppc] [PATCH 05/27] ppc/pnv: change the CPU machine_data presenter type to Object *, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 10/27] ppc/xive: Make XIVE generate the proper interrupt types, Cédric Le Goater, 2019/03/06
- [Qemu-ppc] [PATCH 15/27] ppc/pnv: add a PSI bridge model for POWER9, Cédric Le Goater, 2019/03/06