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[Qemu-ppc] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order |
Date: |
Sun, 10 Mar 2019 19:26:42 +1100 |
From: Mark Cave-Ayland <address@hidden>
When VSX support was initially added, the fpr registers were added at
offset 0 of the VSR register and the vsrl registers were added at offset
1. This is in contrast to the VMX registers (the last 32 VSX registers) which
are stored in host-endian order.
Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also
stored in host endian order to match the VMX registers. This ensures that TCG
vector operations involving mixed VMX and VSX registers will function
correctly.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 4 ++--
target/ppc/internal.h | 8 ++++----
target/ppc/machine.c | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3050982707..8905edbfd0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nregs,
int rx)
static inline int fpr_offset(int i)
{
- return offsetof(CPUPPCState, vsr[i].u64[0]);
+ return offsetof(CPUPPCState, vsr[i].VsrD(0));
}
static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
@@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int
i)
static inline int vsrl_offset(int i)
{
- return offsetof(CPUPPCState, vsr[i].u64[1]);
+ return offsetof(CPUPPCState, vsr[i].VsrD(1));
}
static inline int vsr_full_offset(int i)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 3ebbdf4da4..fb6f64ed1e 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6,
6);
static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
{
- vsr->VsrD(0) = env->vsr[n].u64[0];
- vsr->VsrD(1) = env->vsr[n].u64[1];
+ vsr->VsrD(0) = env->vsr[n].VsrD(0);
+ vsr->VsrD(1) = env->vsr[n].VsrD(1);
}
static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
{
- env->vsr[n].u64[0] = vsr->VsrD(0);
- env->vsr[n].u64[1] = vsr->VsrD(1);
+ env->vsr[n].VsrD(0) = vsr->VsrD(0);
+ env->vsr[n].VsrD(1) = vsr->VsrD(1);
}
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 756b6d2971..a92d0ad3a3 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
- v->u64[0] = qemu_get_be64(f);
+ v->VsrD(0) = qemu_get_be64(f);
return 0;
}
@@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
- qemu_put_be64(f, v->u64[0]);
+ qemu_put_be64(f, v->VsrD(0));
return 0;
}
@@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
- v->u64[1] = qemu_get_be64(f);
+ v->VsrD(1) = qemu_get_be64(f);
return 0;
}
@@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
- qemu_put_be64(f, v->u64[1]);
+ qemu_put_be64(f, v->VsrD(1));
return 0;
}
--
2.20.1
- [Qemu-ppc] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine, (continued)
- [Qemu-ppc] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 30/60] ppc/pnv: fix logging primitives using Ox, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 23/60] ppc/xive: export the TIMA memory accessors, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 28/60] ppc/pnv: introduce a new pic_print_info() operation to the chip model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 27/60] ppc/pnv: introduce a new dt_populate() operation to the chip model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 40/60] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 37/60] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 26/60] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 35/60] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 34/60] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order,
David Gibson <=
- [Qemu-ppc] [PULL 43/60] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 33/60] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 42/60] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 50/60] ppc/pnv: add a OCC model class, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 49/60] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/10