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Re: [Qemu-ppc] [PATCH 3/9] target/ppc: Fix xxbrq, xxbrw
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 3/9] target/ppc: Fix xxbrq, xxbrw |
Date: |
Tue, 7 May 2019 15:21:30 +1000 |
User-agent: |
Mutt/1.11.4 (2019-03-13) |
On Tue, May 07, 2019 at 10:48:05AM +1000, Anton Blanchard wrote:
> Fix a typo in xxbrq and xxbrw where we put both results into the lower
> doubleword.
>
> Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
> helpers for VSR register access")
> Signed-off-by: Anton Blanchard <address@hidden>
Applied, thanks.
> ---
> target/ppc/translate/vsx-impl.inc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
> index d050cc03ed..05b75105be 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1192,7 +1192,7 @@ static void gen_xxbrq(DisasContext *ctx)
> tcg_gen_bswap64_i64(xtl, xbh);
> set_cpu_vsrl(xT(ctx->opcode), xtl);
> tcg_gen_mov_i64(xth, t0);
> - set_cpu_vsrl(xT(ctx->opcode), xth);
> + set_cpu_vsrh(xT(ctx->opcode), xth);
>
> tcg_temp_free_i64(t0);
> tcg_temp_free_i64(xth);
> @@ -1220,7 +1220,7 @@ static void gen_xxbrw(DisasContext *ctx)
> get_cpu_vsrl(xbl, xB(ctx->opcode));
>
> gen_bswap32x4(xth, xtl, xbh, xbl);
> - set_cpu_vsrl(xT(ctx->opcode), xth);
> + set_cpu_vsrh(xT(ctx->opcode), xth);
> set_cpu_vsrl(xT(ctx->opcode), xtl);
>
> tcg_temp_free_i64(xth);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH 1/9] target/ppc: Fix xvxsigdp, Anton Blanchard, 2019/05/06
- [Qemu-ppc] [PATCH 3/9] target/ppc: Fix xxbrq, xxbrw, Anton Blanchard, 2019/05/06
- Re: [Qemu-ppc] [PATCH 3/9] target/ppc: Fix xxbrq, xxbrw,
David Gibson <=
- [Qemu-ppc] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Anton Blanchard, 2019/05/06
Re: [Qemu-ppc] [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Mark Cave-Ayland, 2019/05/10