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QEMU PowerNV decrementer requires a write before it works
From: |
Anton Blanchard |
Subject: |
QEMU PowerNV decrementer requires a write before it works |
Date: |
Thu, 24 Oct 2019 08:29:31 +1100 |
Hi,
Mikey noticed that the PowerNV decrementer doesn't work until it is
written. Is that expected? A test case is below:
powerpc64le-linux-gcc -c test.S
powerpc64le-linux-ld -Ttex=0x0 -o test.elf test.o
powerpc64le-linux-objcopy -O binary test.elf test.bin
qemu-system-ppc64 -M powernv -cpu POWER9 -nographic -bios test.bin
"info registers" shows it looping in the lower loop, ie the
decrementer exception was never taken.
If you build with -DWRITE_DECR:
powerpc64le-linux-gcc -DWRITE_DECR -c test.S
Then it loops in 0x900 as expected.
Thanks,
Anton
--
#include <ppc-asm.h>
/* Load an immediate 64-bit value into a register */
#define LOAD_IMM64(r, e) \
lis r,(e)@highest; \
ori r,r,(e)@higher; \
rldicr r,r, 32, 31; \
oris r,r, (e)@h; \
ori r,r, (e)@l;
#define FIXUP_ENDIAN \
tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
b 191f; /* Skip trampoline if endian is good */ \
.long 0xa600607d; /* mfmsr r11 */ \
.long 0x01006b69; /* xori r11,r11,1 */ \
.long 0x05009f42; /* bcl 20,31,$+4 */ \
.long 0xa602487d; /* mflr r10 */ \
.long 0x14004a39; /* addi r10,r10,20 */ \
.long 0xa64b5a7d; /* mthsrr0 r10 */ \
.long 0xa64b7b7d; /* mthsrr1 r11 */ \
.long 0x2402004c; /* hrfid */ \
191:
.= 0x0
.globl _start
_start:
b 1f
.= 0x10
FIXUP_ENDIAN
b 1f
.= 0x100
1:
FIXUP_ENDIAN
b 2f
#define EXCEPTION(nr) \
.= nr ;\
b .
/* More exception stubs */
EXCEPTION(0x300)
EXCEPTION(0x380)
EXCEPTION(0x400)
EXCEPTION(0x480)
EXCEPTION(0x500)
EXCEPTION(0x600)
EXCEPTION(0x700)
EXCEPTION(0x800)
.= 0x900
1: b 1b
EXCEPTION(0x980)
EXCEPTION(0xa00)
EXCEPTION(0xb00)
EXCEPTION(0xc00)
EXCEPTION(0xd00)
EXCEPTION(0xe00)
EXCEPTION(0xe20)
EXCEPTION(0xe40)
EXCEPTION(0xe60)
EXCEPTION(0xe80)
EXCEPTION(0xf00)
EXCEPTION(0xf20)
EXCEPTION(0xf40)
EXCEPTION(0xf60)
EXCEPTION(0xf80)
EXCEPTION(0x1000)
EXCEPTION(0x1100)
EXCEPTION(0x1200)
EXCEPTION(0x1300)
EXCEPTION(0x1400)
EXCEPTION(0x1500)
EXCEPTION(0x1600)
2:
/* SF, HV, EE, RI, LE */
LOAD_IMM64(r0, 0x9000000000008003)
mtmsrd r0
#ifdef WRITE_DECR
LOAD_IMM64(r0, 0x1000000)
mtdec r0
#endif
1: b 1b
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