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[PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter pa
From: |
David Gibson |
Subject: |
[PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter |
Date: |
Tue, 17 Dec 2019 15:42:32 +1100 |
From: Cédric Le Goater <address@hidden>
The TIMA operations are performed on behalf of the XIVE IVPE sub-engine
(Presenter) on the thread interrupt context registers. The current
operations supported by the model are simple and do not require access
to the controller but more complex operations will need access to the
controller NVT table and to its configuration.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/pnv_xive.c | 4 +--
hw/intc/xive.c | 58 ++++++++++++++++++++++++-------------------
include/hw/ppc/xive.h | 7 +++---
3 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index b2ab2ccc91..95e9de312c 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -1436,7 +1436,7 @@ static void xive_tm_indirect_write(void *opaque, hwaddr
offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_indirect_read(void *opaque, hwaddr offset,
@@ -1444,7 +1444,7 @@ static uint64_t xive_tm_indirect_read(void *opaque,
hwaddr offset,
{
XiveTCTX *tctx = pnv_xive_get_indirect_tctx(PNV_XIVE(opaque));
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
static const MemoryRegionOps xive_tm_indirect_ops = {
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 8e683847bf..9e7e5ea57c 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -144,19 +144,20 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring)
* XIVE Thread Interrupt Management Area (TIMA)
*/
-static void xive_tm_set_hv_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff);
}
-static uint64_t xive_tm_ack_hv_reg(XiveTCTX *tctx, hwaddr offset, unsigned
size)
+static uint64_t xive_tm_ack_hv_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW3_HV_PHYS);
}
-static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_pool_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
uint32_t qw2w2;
@@ -166,13 +167,14 @@ static uint64_t xive_tm_pull_pool_ctx(XiveTCTX *tctx,
hwaddr offset,
return qw2w2;
}
-static void xive_tm_vt_push(XiveTCTX *tctx, hwaddr offset,
+static void xive_tm_vt_push(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
uint64_t value, unsigned size)
{
tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff;
}
-static uint64_t xive_tm_vt_poll(XiveTCTX *tctx, hwaddr offset, unsigned size)
+static uint64_t xive_tm_vt_poll(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff;
}
@@ -315,13 +317,14 @@ static uint64_t xive_tm_raw_read(XiveTCTX *tctx, hwaddr
offset, unsigned size)
* state changes (side effects) in addition to setting/returning the
* interrupt management area context of the processor thread.
*/
-static uint64_t xive_tm_ack_os_reg(XiveTCTX *tctx, hwaddr offset, unsigned
size)
+static uint64_t xive_tm_ack_os_reg(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
return xive_tctx_accept(tctx, TM_QW1_OS);
}
-static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
{
xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
}
@@ -330,8 +333,8 @@ static void xive_tm_set_os_cppr(XiveTCTX *tctx, hwaddr
offset,
* Adjust the IPB to allow a CPU to process event queues of other
* priorities during one physical interrupt cycle.
*/
-static void xive_tm_set_os_pending(XiveTCTX *tctx, hwaddr offset,
- uint64_t value, unsigned size)
+static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned
size)
{
ipb_update(&tctx->regs[TM_QW1_OS], value & 0xff);
xive_tctx_notify(tctx, TM_QW1_OS);
@@ -366,8 +369,8 @@ static void xive_tctx_set_os_cam(XiveTCTX *tctx, uint32_t
qw1w2)
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
}
-static uint64_t xive_tm_pull_os_ctx(XiveTCTX *tctx, hwaddr offset,
- unsigned size)
+static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
{
uint32_t qw1w2;
uint32_t qw1w2_new;
@@ -396,9 +399,11 @@ typedef struct XiveTmOp {
uint8_t page_offset;
uint32_t op_offset;
unsigned size;
- void (*write_handler)(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
- uint64_t (*read_handler)(XiveTCTX *tctx, hwaddr offset, unsigned size);
+ void (*write_handler)(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset,
+ uint64_t value, unsigned size);
+ uint64_t (*read_handler)(XivePresenter *xptr, XiveTCTX *tctx, hwaddr
offset,
+ unsigned size);
} XiveTmOp;
static const XiveTmOp xive_tm_operations[] = {
@@ -444,8 +449,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset,
unsigned size, bool write)
/*
* TIMA MMIO handlers
*/
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size)
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size)
{
const XiveTmOp *xto;
@@ -462,7 +467,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset,
uint64_t value,
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at TIMA
"
"@%"HWADDR_PRIx"\n", offset);
} else {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
}
return;
}
@@ -472,7 +477,7 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset,
uint64_t value,
*/
xto = xive_tm_find_op(offset, size, true);
if (xto) {
- xto->write_handler(tctx, offset, value, size);
+ xto->write_handler(xptr, tctx, offset, value, size);
return;
}
@@ -482,7 +487,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset,
uint64_t value,
xive_tm_raw_write(tctx, offset, value, size);
}
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size)
{
const XiveTmOp *xto;
@@ -500,7 +506,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset,
unsigned size)
"@%"HWADDR_PRIx"\n", offset);
return -1;
}
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -508,7 +514,7 @@ uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset,
unsigned size)
*/
xto = xive_tm_find_op(offset, size, false);
if (xto) {
- return xto->read_handler(tctx, offset, size);
+ return xto->read_handler(xptr, tctx, offset, size);
}
/*
@@ -522,14 +528,14 @@ static void xive_tm_write(void *opaque, hwaddr offset,
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- xive_tctx_tm_write(tctx, offset, value, size);
+ xive_tctx_tm_write(XIVE_PRESENTER(opaque), tctx, offset, value, size);
}
static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
{
XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
- return xive_tctx_tm_read(tctx, offset, size);
+ return xive_tctx_tm_read(XIVE_PRESENTER(opaque), tctx, offset, size);
}
const MemoryRegionOps xive_tm_ops = {
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index b00af98877..97bbcddb38 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -463,9 +463,10 @@ typedef struct XiveENDSource {
#define XIVE_TM_USER_PAGE 0x3
extern const MemoryRegionOps xive_tm_ops;
-void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset, uint64_t value,
- unsigned size);
-uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size);
+void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size);
+uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ unsigned size);
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp);
--
2.23.0
- [PULL 34/88] ppc/xive: Introduce a XiveFabric interface, (continued)
- [PULL 34/88] ppc/xive: Introduce a XiveFabric interface, David Gibson, 2019/12/16
- [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT, David Gibson, 2019/12/16
- [PULL 35/88] ppc/pnv: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, David Gibson, 2019/12/16
- [PULL 33/88] ppc/pnv: Fix TIMA indirect access, David Gibson, 2019/12/16
- [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces, David Gibson, 2019/12/16
- [PULL 29/88] ppc/pnv: Instantiate cores separately, David Gibson, 2019/12/16
- [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper, David Gibson, 2019/12/16
- [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model, David Gibson, 2019/12/16
- [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter,
David Gibson <=
- [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT, David Gibson, 2019/12/16
- [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller, David Gibson, 2019/12/16
- [PULL 39/88] linux-headers: Update, David Gibson, 2019/12/16
- [PULL 42/88] spapr/xive: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler, David Gibson, 2019/12/16
- [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper, David Gibson, 2019/12/16
- [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper, David Gibson, 2019/12/16
- [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models, David Gibson, 2019/12/16
- [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover, David Gibson, 2019/12/16
- [PULL 57/88] xics: Don't deassert outputs, David Gibson, 2019/12/16