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[PULL 69/88] target/ppc: Add SPR TBU40
From: |
David Gibson |
Subject: |
[PULL 69/88] target/ppc: Add SPR TBU40 |
Date: |
Tue, 17 Dec 2019 15:43:03 +1100 |
From: Suraj Jitindar Singh <address@hidden>
The spr TBU40 is used to set the upper 40 bits of the timebase
register, present on POWER5+ and later processors.
This register can only be written by the hypervisor, and cannot be read.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/ppc.c | 13 +++++++++++++
target/ppc/cpu.h | 1 +
target/ppc/helper.h | 1 +
target/ppc/timebase_helper.c | 5 +++++
target/ppc/translate_init.inc.c | 19 +++++++++++++++++++
5 files changed, 39 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 2856d69495..4c5fa29399 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -698,6 +698,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
&tb_env->vtb_offset, value);
}
+void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
+{
+ ppc_tb_t *tb_env = env->tb_env;
+ uint64_t tb;
+
+ tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ tb_env->tb_offset);
+ tb &= 0xFFFFFFUL;
+ tb |= (value & ~0xFFFFFFUL);
+ cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
+ &tb_env->tb_offset, tb);
+}
+
static void cpu_ppc_tb_stop (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e99850c3ae..103bfe9dc2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1310,6 +1310,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env);
void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
+void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 356a14d8a6..cd0dfe383a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -672,6 +672,7 @@ DEF_HELPER_FLAGS_2(store_decr, TCG_CALL_NO_RWG, void, env,
tl)
DEF_HELPER_FLAGS_1(load_hdecr, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_hid0_601, void, env, tl)
DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 2395295b77..703bd9ed18 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -128,6 +128,11 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val)
cpu_ppc_store_vtb(env, val);
}
+void helper_store_tbu40(CPUPPCState *env, target_ulong val)
+{
+ cpu_ppc_store_tbu40(env, val);
+}
+
target_ulong helper_load_40x_pit(CPUPPCState *env)
{
return load_40x_pit(env);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index c850a9d065..d33d65dff7 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -327,6 +327,11 @@ static void spr_write_vtb(DisasContext *ctx, int sprn, int
gprn)
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
}
+static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
+}
+
#endif
#endif
@@ -7853,6 +7858,16 @@ static void gen_spr_power5p_ear(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_power5p_tb(CPUPPCState *env)
+{
+ /* TBU40 (High 40 bits of the Timebase register */
+ spr_register_hv(env, SPR_TBU40, "TBU40",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu40,
+ 0x00000000);
+}
+
#if !defined(CONFIG_USER_ONLY)
static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
{
@@ -8404,6 +8419,7 @@ static void init_proc_power5plus(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
/* env variables */
env->dcache_line_size = 128;
@@ -8516,6 +8532,7 @@ static void init_proc_POWER7(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power7_book4(env);
@@ -8657,6 +8674,7 @@ static void init_proc_POWER8(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power8_tce_address_control(env);
@@ -8847,6 +8865,7 @@ static void init_proc_POWER9(CPUPPCState *env)
gen_spr_power5p_common(env);
gen_spr_power5p_lpar(env);
gen_spr_power5p_ear(env);
+ gen_spr_power5p_tb(env);
gen_spr_power6_common(env);
gen_spr_power6_dbg(env);
gen_spr_power8_tce_address_control(env);
--
2.23.0
- [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, (continued)
- [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, David Gibson, 2019/12/16
- [PULL 51/88] ppc: well form kvmppc_hint_smt_possible error hint helper, David Gibson, 2019/12/16
- [PULL 54/88] spapr: Fold h_cas_compose_response() into h_client_architecture_support(), David Gibson, 2019/12/16
- [PULL 55/88] spapr: Simplify ovec diff, David Gibson, 2019/12/16
- [PULL 49/88] ppc/pnv: Extend XiveRouter with a get_block_id() handler, David Gibson, 2019/12/16
- [PULL 53/88] spapr: Improve handling of fdt buffer size, David Gibson, 2019/12/16
- [PULL 56/88] ppc: Deassert the external interrupt pin in KVM on reset, David Gibson, 2019/12/16
- [PULL 64/88] ppc/pnv: add a PSI bridge model for POWER10, David Gibson, 2019/12/16
- [PULL 69/88] target/ppc: Add SPR TBU40,
David Gibson <=
- [PULL 50/88] ppc/pnv: Dump the XIVE NVT table, David Gibson, 2019/12/16
- [PULL 65/88] ppc/pnv: add a LPC Controller model for POWER10, David Gibson, 2019/12/16
- [PULL 60/88] ppc: Make PPCVirtualHypervisor an incomplete type, David Gibson, 2019/12/16
- [PULL 59/88] ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM, David Gibson, 2019/12/16
- [PULL 70/88] ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes, David Gibson, 2019/12/16
- [PULL 63/88] ppc/psi: cleanup definitions, David Gibson, 2019/12/16
- [PULL 68/88] target/ppc: Add SPR ASDR, David Gibson, 2019/12/16
- [PULL 61/88] target/ppc: Add POWER10 DD1.0 model information, David Gibson, 2019/12/16
- [PULL 75/88] ppc: Drop useless extern annotation for functions, David Gibson, 2019/12/16
- [PULL 62/88] ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machine, David Gibson, 2019/12/16