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[PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip
From: |
David Gibson |
Subject: |
[PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip |
Date: |
Wed, 8 Jan 2020 16:23:00 +1100 |
From: Cédric Le Goater <address@hidden>
POWER8 is the only chip using the XICS interface. Add a "xics" link
and a XICSFabric attribute under this chip to remove the use of
qdev_get_machine()
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 24 +++++++++++++++++++-----
include/hw/ppc/pnv.h | 2 ++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 90e92e82c5..65cba84335 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -802,6 +802,13 @@ static void pnv_init(MachineState *machine)
&error_fatal);
object_property_set_int(chip, machine->smp.cores,
"nr-cores", &error_fatal);
+ /*
+ * The POWER8 machine use the XICS interrupt interface.
+ * Propagate the XICS fabric to the chip and its controllers.
+ */
+ if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
+ object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort);
+ }
object_property_set_bool(chip, true, "realized", &error_fatal);
}
g_free(chip_typename);
@@ -843,12 +850,12 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip,
uint32_t core_id)
static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
+ Pnv8Chip *chip8 = PNV8_CHIP(chip);
Error *local_err = NULL;
Object *obj;
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP,
XICS_FABRIC(qdev_get_machine()),
- &local_err);
+ obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -1002,6 +1009,12 @@ static void pnv_chip_power8_instance_init(Object *obj)
{
Pnv8Chip *chip8 = PNV8_CHIP(obj);
+ object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
+ (Object **)&chip8->xics,
+ object_property_allow_set_link,
+ OBJ_PROP_LINK_STRONG,
+ &error_abort);
+
object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
TYPE_PNV8_PSI, &error_abort, NULL);
@@ -1021,7 +1034,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error
**errp)
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
int i, j;
char *name;
- XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
name = g_strdup_printf("icp-%x", chip->chip_id);
memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
@@ -1037,7 +1049,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error
**errp)
for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
- PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
+ PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
&icp->mmio);
@@ -1053,6 +1065,8 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
Pnv8Psi *psi8 = &chip8->psi;
Error *local_err = NULL;
+ assert(chip8->xics);
+
/* XSCOM bridge is first */
pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
if (local_err) {
@@ -1070,7 +1084,7 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
"bar", &error_fatal);
- object_property_set_link(OBJECT(&chip8->psi), OBJECT(qdev_get_machine()),
+ object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics),
ICS_PROP_XICS, &error_abort);
object_property_set_bool(OBJECT(&chip8->psi), true, "realized",
&local_err);
if (local_err) {
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index f78fd0dd96..56277862dd 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -72,6 +72,8 @@ typedef struct Pnv8Chip {
Pnv8Psi psi;
PnvOCC occ;
PnvHomer homer;
+
+ XICSFabric *xics;
} Pnv8Chip;
#define TYPE_PNV9_CHIP "pnv9-chip"
--
2.24.1
- [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset, (continued)
- [PULL 02/26] target/ppc: Handle AIL=0 in ppc_excp_vector_offset, David Gibson, 2020/01/08
- [PULL 10/26] ppc440_bamboo.c: remove label from bamboo_load_device_tree(), David Gibson, 2020/01/08
- [PULL 08/26] ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG, David Gibson, 2020/01/08
- [PULL 07/26] spapr/xive: Use device_class_set_parent_realize(), David Gibson, 2020/01/08
- [PULL 16/26] spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router, David Gibson, 2020/01/08
- [PULL 25/26] ppc/pnv: check return value of blk_pwrite(), David Gibson, 2020/01/08
- [PULL 09/26] spapr.c: remove 'out' label in spapr_dt_cas_updates(), David Gibson, 2020/01/08
- [PULL 18/26] ppc/pnv: Add an "nr-threads" property to the base chip class, David Gibson, 2020/01/08
- [PULL 15/26] pnv/xive: Use device_class_set_parent_realize(), David Gibson, 2020/01/08
- [PULL 22/26] pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr, David Gibson, 2020/01/08
- [PULL 14/26] ppc/pnv: Introduce a "xics" property under the POWER8 chip,
David Gibson <=
- [PULL 19/26] ppc/pnv: Add a "pnor" const link property to the BMC internal simulator, David Gibson, 2020/01/08
- [PULL 13/26] ppc/pnv: Introduce a "xics" property alias under the PSI model, David Gibson, 2020/01/08
- [PULL 17/26] xive: Use the XIVE fabric link under the XIVE router, David Gibson, 2020/01/08
- [PULL 21/26] spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr, David Gibson, 2020/01/08
- [PULL 06/26] mos6522: remove anh register, David Gibson, 2020/01/08
- [PULL 11/26] ppc/pnv: Drop "num-chips" machine property, David Gibson, 2020/01/08
- [PULL 03/26] linux-headers: Update, David Gibson, 2020/01/08
- [PULL 12/26] spapr/xive: remove redundant check in spapr_match_nvt(), David Gibson, 2020/01/08
- [PULL 20/26] xive: Add a "presenter" link property to the TCTX object, David Gibson, 2020/01/08
- [PULL 26/26] ppc/pnv: fix check on return value of blk_getlength(), David Gibson, 2020/01/08