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Re: [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB ent
From: |
David Gibson |
Subject: |
Re: [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry |
Date: |
Thu, 20 Feb 2020 14:13:26 +1100 |
On Wed, Feb 19, 2020 at 11:34:22AM -0300, Fabiano Rosas wrote:
> David Gibson <address@hidden> writes:
>
>
> Hi, just a nitpick, feel free to ignore.
>
> > When in VRMA mode (i.e. a guest thinks it has the MMU off, but the
> > hypervisor is still applying translation) we use a special SLB entry,
> > rather than looking up an SLBE by address as we do when guest translation
> > is on.
> >
> > We build that special entry in ppc_hash64_update_vrma() along with some
> > logic for handling some non-VRMA cases. Split the actual build of the
> > VRMA SLBE into a separate helper and streamline it a bit.
> >
> > Signed-off-by: David Gibson <address@hidden>
> > ---
> > target/ppc/mmu-hash64.c | 79 ++++++++++++++++++++---------------------
> > 1 file changed, 38 insertions(+), 41 deletions(-)
> >
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index 170a78bd2e..06cfff9860 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -789,6 +789,39 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
> > }
> > }
> >
> > +static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
> > +{
> > + CPUPPCState *env = &cpu->env;
> > + target_ulong lpcr = env->spr[SPR_LPCR];
> > + uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
> > + target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) &
> > SLB_VSID_LLP_MASK);
> > + int i;
> > +
> > + /*
> > + * Make one up. Mostly ignore the ESID which will not be needed
> > + * for translation
> > + */
>
> I find this comment a bit vague. I suggest we either leave it behind or
> make it more precise. The ISA says:
>
> "translation of effective addresses to virtual addresses use the SLBE
> values in Figure 18 instead of the entry in the SLB corresponding to the
> ESID"
Yeah, it wasn't very helpful in its initial location, and it's even
less helpful here. I've dropped it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode, (continued)
- [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode, David Gibson, 2020/02/18
- [PATCH v3 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU, David Gibson, 2020/02/18
- [PATCH v3 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS], David Gibson, 2020/02/18
- [PATCH v3 09/12] target/ppc: Correct RMLS table, David Gibson, 2020/02/18
- [PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10, David Gibson, 2020/02/18
- [PATCH v3 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9, David Gibson, 2020/02/18
- [PATCH v3 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/02/18
- [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry, David Gibson, 2020/02/18
- [PATCH v3 12/12] target/ppc: Don't store VRMA SLBE persistently, David Gibson, 2020/02/18
- [PATCH v3 07/12] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/02/18
- Re: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling, no-reply, 2020/02/18
- Re: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling, David Gibson, 2020/02/18