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[PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement P
From: |
matheus . ferst |
Subject: |
[PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI |
Date: |
Mon, 17 May 2021 17:50:14 -0300 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 8 ++++
target/ppc/insn64.decode | 12 ++++++
target/ppc/translate.c | 29 --------------
target/ppc/translate/fixedpoint-impl.c.inc | 44 ++++++++++++++++++++++
4 files changed, 64 insertions(+), 29 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a3a8ae06bf..e7c062d8b4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -16,3 +16,11 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+&D rt ra si:int64_t
+@D ...... rt:5 ra:5 si:s16 &D
+
+### Fixed-Point Arithmetic Instructions
+
+ADDI 001110 ..... ..... ................ @D
+ADDIS 001111 ..... ..... ................ @D
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index a38b1f84dc..1965088915 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -16,3 +16,15 @@
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
+
+# Format MLS:D and 8LS:D
+&PLS_D rt ra si:int64_t r:bool
+%pls_si 32:s18 0:16
+@PLS_D ...... .. ... r:1 .. .................. \
+ ...... rt:5 ra:5 ................ \
+ &PLS_D si=%pls_si
+
+### Fixed-Point Arithmetic Instructions
+
+PADDI 000001 10 0--.-- .................. \
+ 001110 ..... ..... ................ @PLS_D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 64d6acb078..5bf9001141 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1846,19 +1846,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
/* addze addze. addzeo addzeo.*/
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
-/* addi */
-static void gen_addi(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* li case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm);
- }
-}
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
@@ -1878,20 +1865,6 @@ static void gen_addic_(DisasContext *ctx)
gen_op_addic(ctx, 1);
}
-/* addis */
-static void gen_addis(DisasContext *ctx)
-{
- target_long simm = SIMM(ctx->opcode);
-
- if (rA(ctx->opcode) == 0) {
- /* lis case */
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
- } else {
- tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
- cpu_gpr[rA(ctx->opcode)], simm << 16);
- }
-}
-
/* addpcis */
static void gen_addpcis(DisasContext *ctx)
{
@@ -7903,10 +7876,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000,
PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
-GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index be75085cee..344a3ed54b 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -16,3 +16,47 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+/*
+ * Incorporate CIA into the constant when R=1.
+ * Validate that when R=1, RA=0.
+ */
+static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
+{
+ d->rt = a->rt;
+ d->ra = a->ra;
+ d->si = a->si;
+ if (a->r) {
+ if (unlikely(a->ra != 0)) {
+ gen_invalid(ctx);
+ return false;
+ }
+ d->si += ctx->cia;
+ }
+ return true;
+}
+
+static bool trans_ADDI(DisasContext *ctx, arg_D *a)
+{
+ if (a->ra) {
+ tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si);
+ } else {
+ tcg_gen_movi_tl(cpu_gpr[a->rt], a->si);
+ }
+ return true;
+}
+
+static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a)
+{
+ arg_D d;
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+ return trans_ADDI(ctx, &d);
+}
+
+static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
+{
+ a->si <<= 16;
+ return trans_ADDI(ctx, a);
+}
--
2.25.1
- [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn, (continued)
- [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn, matheus . ferst, 2021/05/17
- [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check, matheus . ferst, 2021/05/17
- [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions, matheus . ferst, 2021/05/17
- [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn, matheus . ferst, 2021/05/17
- [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns, matheus . ferst, 2021/05/17
- [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI,
matheus . ferst <=
- [PATCH v5 13/23] target/ppc: Implement PNOP, matheus . ferst, 2021/05/17
- [PATCH v5 14/23] TCG: add tcg_constant_tl, matheus . ferst, 2021/05/17
- [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree, matheus . ferst, 2021/05/17
- [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions, matheus . ferst, 2021/05/17
- [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree, matheus . ferst, 2021/05/17