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Re: [PATCH v2] target/ppc: Fix load endianness for lxvwsx/lxvdsx
From: |
David Gibson |
Subject: |
Re: [PATCH v2] target/ppc: Fix load endianness for lxvwsx/lxvdsx |
Date: |
Wed, 19 May 2021 10:42:54 +1000 |
On Tue, May 18, 2021 at 03:30:20PM +0200, Giuseppe Musacchio wrote:
> TARGET_WORDS_BIGENDIAN may not match the machine endianness if that's a
> runtime-configurable parameter.
>
> Fixes: bcb0b7b1a1c05707304f80ca6f523d557816f85c
> Fixes: afae37d98ae991c0792c867dbd9f32f988044318
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/212
>
> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
That looks more like it. Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/translate/vsx-impl.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.c.inc
> b/target/ppc/translate/vsx-impl.c.inc
> index b817d31260..57a7f73bba 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -139,7 +139,7 @@ static void gen_lxvwsx(DisasContext *ctx)
> gen_addr_reg_index(ctx, EA);
>
> data = tcg_temp_new_i32();
> - tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
> + tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UL));
> tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16,
> data);
>
> tcg_temp_free(EA);
> @@ -162,7 +162,7 @@ static void gen_lxvdsx(DisasContext *ctx)
> gen_addr_reg_index(ctx, EA);
>
> data = tcg_temp_new_i64();
> - tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
> + tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
> tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16,
> data);
>
> tcg_temp_free(EA);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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