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[PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception*
From: |
David Gibson |
Subject: |
[PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception* |
Date: |
Wed, 19 May 2021 22:51:18 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
There are other valid settings for is_jmp besides
DISAS_NEXT and DISAS_NORETURN, so eliminating that
dichotomy from ppc_tr_translate_insn is helpful.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210512185441.3619828-4-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d6a8a04380..ac0c0e5b2c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -264,7 +264,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t
excp, uint32_t error)
gen_helper_raise_exception_err(cpu_env, t0, t1);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception(DisasContext *ctx, uint32_t excp)
@@ -281,7 +282,8 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
@@ -293,7 +295,8 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t
excp,
t0 = tcg_const_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
- ctx->exception = (excp);
+ ctx->exception = excp;
+ ctx->base.is_jmp = DISAS_NORETURN;
}
/*
@@ -339,6 +342,7 @@ static void gen_debug_exception(DisasContext *ctx)
t0 = tcg_const_i32(EXCP_DEBUG);
gen_helper_raise_exception(cpu_env, t0);
tcg_temp_free_i32(t0);
+ ctx->base.is_jmp = DISAS_NORETURN;
}
static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
@@ -9183,7 +9187,6 @@ static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase, CPUState *cs,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
gen_debug_exception(ctx);
- dcbase->is_jmp = DISAS_NORETURN;
/*
* The address covered by the breakpoint must be included in
* [tb->pc, tb->pc + tb->size) in order to for it to be properly
@@ -9213,18 +9216,19 @@ static void ppc_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
ok = decode_legacy(cpu, ctx, insn);
if (!ok) {
gen_invalid(ctx);
- ctx->base.is_jmp = DISAS_NORETURN;
}
#if defined(DO_PPC_STATISTICS)
handler->count++;
#endif
+
/* Check trace mode exceptions */
if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
(ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
ctx->exception != POWERPC_SYSCALL &&
ctx->exception != POWERPC_EXCP_TRAP &&
- ctx->exception != POWERPC_EXCP_BRANCH)) {
+ ctx->exception != POWERPC_EXCP_BRANCH &&
+ ctx->base.is_jmp != DISAS_NORETURN)) {
uint32_t excp = gen_prep_dbgex(ctx);
gen_exception_nip(ctx, excp, ctx->base.pc_next);
}
@@ -9235,14 +9239,20 @@ static void ppc_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
}
- ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
- DISAS_NEXT : DISAS_NORETURN;
+ if (ctx->base.is_jmp == DISAS_NEXT
+ && ctx->exception != POWERPC_EXCP_NONE) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ if (ctx->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+
if (ctx->exception == POWERPC_EXCP_NONE) {
gen_goto_tb(ctx, 0, ctx->base.pc_next);
} else if (ctx->exception != POWERPC_EXCP_BRANCH) {
--
2.31.1
- [PULL 04/48] target/ppc: renamed SPR registration functions, (continued)
- [PULL 04/48] target/ppc: renamed SPR registration functions, David Gibson, 2021/05/19
- [PULL 08/48] target/ppc: moved ppc_store_lpcr to misc_helper.c, David Gibson, 2021/05/19
- [PULL 09/48] hw/ppc: moved has_spr to cpu.h, David Gibson, 2021/05/19
- [PULL 10/48] target/ppc: turned SPR R/W callbacks not static, David Gibson, 2021/05/19
- [PULL 11/48] target/ppc: isolated cpu init from translation logic, David Gibson, 2021/05/19
- [PULL 07/48] target/ppc: moved function out of mmu-hash64, David Gibson, 2021/05/19
- [PULL 16/48] target/ppc: Add cia field to DisasContext, David Gibson, 2021/05/19
- [PULL 17/48] target/ppc: Split out decode_legacy, David Gibson, 2021/05/19
- [PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c, David Gibson, 2021/05/19
- [PULL 20/48] target/ppc: Remove special case for POWERPC_EXCP_TRAP, David Gibson, 2021/05/19
- [PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception*,
David Gibson <=
- [PULL 22/48] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}, David Gibson, 2021/05/19
- [PULL 06/48] hw/ppc: moved hcalls that depend on softmmu, David Gibson, 2021/05/19
- [PULL 12/48] target/ppc: created ppc_{store, get}_vscr for generic vscr usage, David Gibson, 2021/05/19
- [PULL 05/48] target/ppc: move SPR R/W callbacks to translate.c, David Gibson, 2021/05/19
- [PULL 28/48] target/ppc: Remove DisasContext.exception, David Gibson, 2021/05/19
- [PULL 13/48] target/ppc: updated vscr manipulation in machine.c, David Gibson, 2021/05/19
- [PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c, David Gibson, 2021/05/19
- [PULL 19/48] target/ppc: Remove special case for POWERPC_SYSCALL, David Gibson, 2021/05/19
- [PULL 21/48] target/ppc: Simplify gen_debug_exception, David Gibson, 2021/05/19
- [PULL 27/48] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN, David Gibson, 2021/05/19